ISL6115 Intersil Corporation, ISL6115 Datasheet - Page 4

• Manufacturer Part Number: ISL6115
• Description: Power Distribution Controllers
• Manufacturer: Intersil Corporation

Description and Operation
The members of this family are single power supply
distribution controllers for generic hot swap applications
across the +2.5V to +12V supply range. The ISL6115 is
targeted for +12V switching applications whereas the
ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the
ISL6120 for +2.5V applications. Each IC has a hardwired
undervoltage (UV) threshold level approximately 17% lower
than the stated voltages.
These ICs feature a highly accurate programmable
overcurrent (OC) detecting comparator, programmable
current regulation (CR) with programmable time delay to
latch off, and programmable soft start turn-on ramp all set
with a minimum of external passive components. The ICs
also include severe OC protection that immediately shuts
down the MOSFET switch should a rapid load current
transient such as a near dead short cause the CR Vth to
exceed the programmed level by 150mV. Additionally, the
ICs have an UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once the IC is
biased, monitoring and reporting any UV condition on the
ISEN pin.
Upon initial power up, the IC can either isolate the voltage
supply from the load by holding the external N-Channel
MOSFET switch off or apply the supply rail voltage directly to
the load for true hot swap capability. The PWRON pin must
be pulled low for the device to isolate the power supply from
the load by holding the external N-channel MOSFET off.
With the PWRON pin held high or floating the IC will be in
true hot swap mode. In both cases the IC turns on in a soft
start mode protecting the supply rail from sudden in-rush
current.
At turn-on, the external gate capacitor of the N-Channel
MOSFET is charged with a 10µA current source resulting in
a programmable ramp (soft start turn-on). The internal
ISL6115 charge pump supplies the gate drive for the 12V
supply switch driving that gate to ~V
three ICs the gate drive voltage is limited to the chip bias
voltage, VDD.
Load current passes through the external current sense
resistor. When the voltage across the sense resistor exceeds
the user programmed CR voltage threshold value, (See Table
1 for R
current regulation threshold voltage, V
its current regulation mode. At this time, the time-out capacitor,
on C
controller enters the current limit time to latch-off period. The
length of the current limit time to latch-off duration is set by the
value of a single external capacitor (see Table 2 for CTIM
capacitor value and resulting nominal current limited time out
to latch-off duration) placed from the CTIM pin (pin 6) to
ground. The programmed current level is held until either the
OC event passes or the time out period expires. If the former
TIM
ISET
pin is charged with a 20µA current source and the
programming resistor value and resulting nominal
4
DD
CR
+5V, for the other
ISL6115, ISL6116, ISL6117, ISL6120
) the controller enters
is the case then the N-Channel MOSFET is fully enhanced
and the C
1.87V, signaling that the time out period has expired an
internal latch is set whereby the FET gate is quickly pulled to
0V turning off the N-Channel MOSFET switch, isolating the
faulty load.
NOTE: Nominal Vth = R
NOTE: Nominal time-out period = C
This IC responds to a severe overcurrent load (defined as a
voltage across the sense resistor >150mV over the OC Vth set
point) by immediately, driving the N-Channel MOSFET gate to
0V in about 10µs. The gate voltage is then slowly ramped up
turning on the N-Channel MOSFET to the programmed current
regulation level, this is the start of the time out period.
Upon an UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic or VDD supply. This
pin is an UV fault indicator. For an OC latch off indication,
monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to
VDD once the time out period expires.
See Figures 12 to 16 for waveforms relevant to text.
The IC is reset after an OC latch-off condition by a low level
on the PWRON pin and is turned on by the PWRON pin
being driven high.
Application Considerations
During the soft start and the time-out delay duration with the
IC in its current limit mode, the V
MOSFET is reduced driving the MOSFET switch into a (linear
region) high r
limit and the timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or destroyed
due to excessive internal power dissipation. Refer to the
MOSFET SOA information in the manufacturers data sheet.
When driving particularly large capacitive loads a longer soft
start time to prevent current regulation upon charging and a
short CR time may offer the best application solution relative
to reliability and FET MTF.
Physical layout of R
possibility of false overcurrent occurrences. Ideally trace
routing between the R
C
TIM
0.022µF
0.047µF
CAPACITOR
R
0.1µF
ISET
TIM
4.99kΩ
2.5kΩ
10kΩ
750Ω
RESISTOR
DS(ON)
capacitor is discharged. Once CTIM charges to
state. Strike a balance between the CR
SENSE
ISET
SENSE
NOMINAL CURRENT LIMITED PERIOD
TABLE 1.
TABLE 2.
x 20µA.
resistor is critical to avoid the
resistors and the IC is as direct
GS
TIM
of the external N-Channel
x 93kΩ.
NOMINAL OC VTH
4.4ms
9.3ms
2ms
200mV
100mV
50mV
15mV