ISL1208 Intersil Corporation, ISL1208 Datasheet - Page 12

• Manufacturer Part Number: ISL1208
• Manufacturer: Intersil Corporation

FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
Table 4 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F
backup mode (i.e. V
FOBATB is set to “1” the F
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See Typical Performance Curves: I
LPMODE ON & OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
FREQUENCY,
BAT
DD
DD
32768
F
< V
< V
4096
1024
1/16
1/32
supply will be used when V
1/2
1/4
1/8
OUT
64
32
16
TABLE 4. FREQUENCY SELECTION OF F
0
8
4
2
1
TRIP
BAT
. With LPMODE = “1”, the device will be in low
- V
UNITS
BATHYS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
BAT
BAT
. There is a supply current saving of
power source active). When the
FO3
OUT
supply will be used when
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
12
OUT
/IRQ pin is disabled during
OUT
DD
/IRQ pin during battery
DD
/IRQ pin is enabled
FO2
< V
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
vs V
OUT
BAT
CC
- V
pin. See
FO1
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DD
with
BATHYS
PIN
= 5V.
OUT
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
and
pin.
ISL1208
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
tied low until the ALM status bit is cleared to “0”.
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
IM BIT
0
1
X1
X2
FIGURE 11. DIAGRAM OF ATR
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
LOAD
C
C
X1
X2
INTERRUPT/ALARM FREQUENCY
X1
is changed via two digitally
and C
OUT
X2
, connected from the X1
Oscillator
pin when the RTC is
Crystal
OUT
LOAD
pin will be
,
FN8085.2