SDA9270 Infineon Technologies Corporation, SDA9270 Datasheet
SDA9270
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SDA9270 Summary of contents
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ICs for Consumer Electronics Field Mixer SDA 9270 Data Sheet 01.96 ...
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SDA 9270 Revision History: Previous Version: Page Edition 01.96 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Field Mixer Preliminary Data 1 Introduction The Field Mixer SDA 9270 is an add-on component for the Siemens MEGAVISION IC set which enables the system to reduce large area and line flickering of interlaced TV standards. 1.1 Features • High ...
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Block Diagram Semiconductor Group 5 SDA 9270 ...
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Pin Configuration Semiconductor Group 6 SDA 9270 ...
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Pin Description Pin No. Name V 10, 30, 47, 54 11, 31, 48, 55 80,1 UVA0 .. 7 I/TTL YA0 .. UVB0 .. 7 I/TTL ...
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Pin Description (cont’d) Pin No. Name 68 BLN3 69 VS3 72 RENA 73 OEBA S: supply, I: input, 2 System Description The device generates at its output an opportune sequence of 100/120 Hz fields derived by processing the field A ...
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Input Data Format The SDA 9270 accepts for the input channels A and B two different input formats (I 2 C-Bus : INFOR) with two possible sample frequency relations (B-Y) : (R-Y). The representation of the ...
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Output Data Format The data format for the output channel Q will be a 4:2:2 parallel format in 2’s complement code representation signal component ab Semiconductor Group Data 4:2:2 Parallel Pin YQ7 ...
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Field Interpolation and Switching In order to reduce the annoying line and edge flickering a frame rate upconversion is implemented. The upconversion includes a combination of interpolation algorithms which are determined via I picture motion content. The field interpolation ...
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A second 25 Hz frame sync signal is needed in the interpolation and switching block and in the VS3 pulse generation block for assuring an output data sequence of the channel Q synchronized with the VS3 pulse. As reference signals ...
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After switching on the IC (RES=0), all bits are set to defined states. Particularly: Register Default Value Semiconductor ...
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C-Bus Commands I Sub- add. (Hex LINFRA PIXLIN 01 0 INCODL 02 ZMMODE1 ZMMODE0 03 RDMODE1 RDMODE0 04 EDCONST1 EDCONST0 05 CFHENA07 CFHENA06 06 CFHENA17 CFHENA16 07 CFHENB07 CFHENB06 08 CFSCHA007 CFSCHA006 CFSCHA005 CFSCHA004 CFSCHA003 ...
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C-Bus Commands (cont’d) I Sub- add. (Hex CFSCHB117 CFSCHB116 CFSCHB115 CFSCHB114 CFSCHB113 CFSCHB112 CFSCHB111 CFSCHB110 10 MDTHL21 MDTHL20 11 MDTHU21 MDTHU20 Semiconductor Group Data ...
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Detailed Description Bit Name Function D7 LINFRA Lines per frame PIXLIN Pixels per line D5...D3 WRMODE* Write Mode: 000 : Normal operation: field memory A and field memory B 001 ...
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Bit Name D6 INCODL D5 INCODC D4 INFOR D3 FALLBACK D2...D0 FIWIN Semiconductor Group Subaddress 01 Function Coding of luminance input data: 0: positive dual code (default value) 1: 2’s complement Coding of chrominance input data: 0: positive dual code ...
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Bit Name D7..D6 ZMMODE D3..D2 INTMODLL D1..D0 INTMODCL Semiconductor Group Subaddress 02 Function zoom mode (enabled only if pin and RDMODE = 00) 00: field sequence at output Q: AABB (default value) 01: field sequence at output ...
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Bit Name D7..D6 RDMODE D3..D2 INTMODLM D1..D0 INTMODCM Semiconductor Group Subaddress 03 Function read mode 00: both inputs are used (interpolation enabled (default value) 01: only input A is used (without interpolation) 10: only input B ...
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Bit Name D7..D6 EDCONST D3..D2 INTMODLH D1..D0 INTMODCH Bit Name D7..D0 CFHENA0 Bit Name D7..D0 CFHENA1 Semiconductor Group Subaddress 04 Function edge detector gain factor 00: 2 01: 3 (default value) 10: 4 11: 5 luminance interpolation mode, high degree ...
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Bit Name D7..D0 CFHENB0 Bit Name D7..D0 CFSCHA00 Bit Name D7..D0 CFSCHA10 Bit Name D7..D0 CFSCHA01 Bit Name D7..D0 CFSCHA11 Bit Name D7..D0 CFSCHB00 Semiconductor Group Subaddress 07 Function Hentschel algorithm, 8-bit coefficient b (default value Subaddress ...
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Bit Name D7..D0 CFSCHB10 Bit Name D7..D0 CFSCHB01 Bit Name D7..D0 CFSCHB11 Bit Name D7..D6 MDTHL2 D5..D4 MDTHL1 D2..D0 MDBLTH Semiconductor Group Subaddress 0D Function Schröder algorithm, 8-bit coefficient b (default value Subaddress 0E Function Schröder algorithm, ...
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Bit Name D7..D6 MDTHU2 D5..D4 MDTHU1 D3..D2 MDTHM2 D1..D0 MDTHM1 Bit Name D5..D0 HYTHL1 Semiconductor Group Subaddress 11 Function threshold for high degree of motion (small blocks) 00: 384 01: 512 (default value) 10: 640 11: 768 threshold for high ...
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Bit Name D5..D0 HYTHL2 Bit Name D5..D0 HYTHH1 Bit Name D5..D0 HYTHH2 Semiconductor Group Subaddress 13 Function hysteresis threshold, low degree of motion (small blocks) 000000: 1 000001: 1 000010 111111: 63 (default value 011000) Subaddress 14 Function ...
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Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Soldering time Input voltage Output voltage Supply voltages Supply voltage Differentials Total power dissipation ESD protection Latch-up protection All voltages listed are referenced to ...
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Recommended Operating Conditions Parameter Supply voltages Ambient temperature All TTL Inputs High-level input voltage Low-level input voltage All TTL outputs High-level output voltage Low-level output voltage Clock TTL Inputs CLL, SCA, SCAD Clock frequency Low time High time Rise ...
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Recommended Operating Conditions (cont’d) Parameter Hold time DATA SDA/SCL rise times SDA/SCL fall times Set-up time stop condition Low-level output current Note: Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values ...
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Characteristics (Assuming Recommended Operating Conditions) Parameter Average supply current All Digital Inputs (including I/O inputs) Input capacitance Input leakage current TTL Inputs: YA, YB, UVA, UVB (referenced to SCA) Set-up time Input hold time TTL Inputs: REN, SACIN, SARIN ...
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Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter TTL Outputs: OEBA, OEBB (referenced to SCAD) Hold time Delay time Input/Output: SDA (referenced to SCL; Open Drain Output) Low-level output voltage Note: The listed characteristics are ensured over the operating range ...
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Application Information Semiconductor Group 30 SDA 9270 ...
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Waveforms Timing Diagram Data Input/Output Referenced to the Clock Timing Diagram Clock Skew SCA - CLL Semiconductor Group 31 SDA 9270 ...
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Package Outlines P-MQFP-80-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 32 SDA 9270 Dimensions in mm ...
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Semiconductor Group 33 SDA 9270 ...