SDA4335 Infineon Technologies Corporation, SDA4335 Datasheet - Page 14

• Manufacturer Part Number: SDA4335
• Description: PLL Frequency Synthesizer, if Counter, 7 Bit ADC, 7 & 4 Bit DAC
• Manufacturer: Infineon Technologies Corporation

Specification
SDA 4335
The SDA 4335 is a FM car radio PLL synthesizer system with IF counter for STS, a 2 channel multi-
plexed 7 bit ADC, a 7 bit DAC- and a 4 bit DAC multifunctional output.
2
The serial bus is switchable between I
C and 3 Wire bus mode.
The 7 bit A/D converter has two input channels and works as successive approximation converter.
The conversion time for both input signals is t = 32 s. The 7-bit digital-words from both channels
(14 bit) are read out together via bus into two bytes with the read subadress 82H.
The input voltage range for both channels is 0...VREFD5V.
For FM-mode the center frequency is adjustable in 128 steps (6.25kHz for standard IF-frequency/
12.5kHz for double IF-frequency) from 10.40MHz...11.19375MHz (standard) /
20.80MHz ... 22.3875MHz (double).
The gate-time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted
count value, the window is adjustable in 5 steps from +/- (250Hz...4kHz).
For AM-mode the center frequency is adjustable in 128 steps (1kHz) from 384kHz ... 511kHz.
Mode is selectable by bus. In FM-mode the input IF_AM is going low with a internally NMOS Open
drain transistor. In AM-mode the input IF_FM is going low with a internally NMOS Opendrain
transistor.
The gate-time is adjustable in 7 steps from 1ms...64ms and the tolerance of the accepted
count value, the window is adjustable in 5 steps from +/- (250Hz...4kHz).
The results IF_CENT and IF_WINDOW are read out via bus (read-subadress 82H). The result
IF_CENT is optional avialable on pin IFC_SD set by bus.
If the IF frequency into the preselected window, IF_CENT goes from high to lo level.
The IF frequency is outside the preselected window, IF_CENT is high. The bit IF_WINDOW is a hint
IF-frequency is to low (IF_WINDOW=high) or is to high (IF_WINDOW=low).
In addition to the frequency measurement, thresholds for ADC_IN1 and ADC_IN2 voltages can be
programmed via bus (subaddress 0BH). IF_CENT will only go to low level in case fo ADC_IN1 and
ADC_IN2 voltages are beyond the thresholds and the frequency is inside the window.
When setting the thresholds to zero ADC_IN1 and ADC_IN2 evaluation is disabled.
A master crystal oscillator provides all necessary clock frequencies for the whole IC. A 61.5 MHz
crystal is used in 3rd harmonic mode.
The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A converter.
The crystal frequency is used as reference frequency for the PLL oscillator and IF counter. It is also
used as clock for the ADC. Finally the crystal frequency divided by 6 (10.25 MHz) is
available at a pin as low pass filtered voltage. It can be disabled with the serial bus.
PORT1 is a NMOS Open drain output,
PORT2_STEREO and IFC_SD are NMOS Open drain outputs in port mode or inputs set by bus.
PORT_7BIT / PORT_4BIT are multifunctionaly DAC outputs with a output voltage range from
V
= 0...VREFD5V, with a resolution from 7 bit and 4 bit.
out
2
The SDA 4335 supports the I
C bus protocol (2 wire) or 3 Wire bus protocol operation
2
selectable by pin 7: BUS_MODE (I
C=low, 3W=high). All bus pins ( BUS_MODE, SCL, SDA,
BUS_ENA) are Schmitt-triggered input buffer for 3V or 5V C.
The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to
high transition of CLK and is shifted out (read mode) on the high to low transition of CLK.
Semiconductor Group
14
21.5.99