BSP-15 Equator Technologies, BSP-15 Datasheet - Page 65

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BSP-15

Manufacturer Part Number
BSP-15
Description
Broadband Signal Processor
Manufacturer
Equator Technologies
Datasheet

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September 6, 2002
Table 6-8 PCI interface timing parameters
a.
Table 6-9 PCI measurement conditions
t
t
t
clk
t
t
t
t
t
t
t
t
t
t
V
V
V
V
V
V
Input signal slew rate
pci_clk
high
low
su(bus)
su(ptp)
val(bus)
val(ptp)
on
off
h
rst
rst-clk
rst-off
max
test
tfall
th
tl
trise
Symbol
Symbol
a
slew
pci_rst_ is asserted and de-asserted asynchronously with respect to pci_clk. All output drivers are floated
when pci_rst_ is active.
clock cycle time
clock high time
clock low time
clock slew rate
input set up time to clk, bussed signals
input set up time to clk, point-to-point signals
clk to signal valid delay, bussed signals
clk to signal valid delay, point to point signal
float to active delay
active to float delay
input hold time from clock
reset active time after power stable
reset active time after clk stable
reset active to output float delay
Description
Value
0.615 VddI/O
0.285 VddI/O
0.4 VddI/O
0.4 VddI/O
0.6 VddI/O
0.2 VddI/O
1.5
HWR.BSP15.DS.REV.H
V
V
V
V
V
V
V/ns
Unit
Min
500
100
1.5
15
6
6
3
5
2
2
2
1
-
-
BSP-15 Processor Datasheet
Max
14
40
30
4
6
6
-
-
-
-
-
-
-
-
Unit
V/ns
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
53

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