PIC12C508A Microchip Technology, PIC12C508A Datasheet - Page 42

• Manufacturer Part Number: PIC12C508A
• Description: 8-Pin/ 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC12C5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
8.5
In the PIC12C5XX, DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows V
min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (V
level. Thus, programming GP3/MCLR/V
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the GP3/
MCLR/V
The Device Reset time delay will vary from chip to chip
due to V
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.
DS40139E-page 42
INTERNAL RESET
INTERNAL POR
DRT TIME-OUT
PP
DD
Device Reset Timer (DRT)
pin as a general purpose input.
, temperature, and process variation. See
MCLR
V
DD
When V
this example, the chip will reset properly if, and only if, V1
DD
rises slowly, the T
DD
to rise above V
PP
DRT
as MCLR
T
IH
DRT
MCLR)
time-out expires long before V
V1
DD
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The
programming the configuration bit WDTE as a ’0’
(Section 8.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.
TABLE 8-5:
Configuration
IntRC &
ExtRC
XT & LP
Oscillator
WDT
V
Watchdog Timer (WDT)
DD
DD
min.
has reached its final value. In
can
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
18 ms (typical)
be
POR Reset
DD
): SLOW V
permanently
1999 Microchip Technology Inc.
DD
300 µs (typical)
18 ms (typical)
Subsequent
RISE TIME
disabled
Resets
by