ADCLK944 Analog Devices, ADCLK944 Datasheet
ADCLK944
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ADCLK944 Summary of contents
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... CC The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to V tial output swing of 1.6 V. The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of REF −40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... ADCLK944 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Clock Inputs and Outputs ........................................................... 3 Timing Characteristics ................................................................ 3 Power .............................................................................................. 4 Absolute Maximum Ratings ............................................................ 5 Determining Junction Temperature .......................................... 5 REVISION HISTORY 3/10—Revision 0: Initial Version ESD Caution...................................................................................5 Thermal Performance ...................................................................5 Pin Configuration and Function Descriptions ..............................6 ...
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... Rev Page www.DataSheet4U.com ADCLK944 Unit Test Conditions/Comments V V p-p ±1.7 V between input pins pF Ω Ω kΩ V open T μA V Load = 50 Ω − 2 Load = 50 Ω − ...
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... ADCLK944 POWER Table 3. Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current 1 Power Supply Rejection 2 Output Swing Supply Rejection 1 Change in t per change Change in output swing per change Symbol Min Typ Max V − ...
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... PCB JA can be used for a first-order approx- JA using the following equation (θ × the ambient temperature (°C). A are provided in Table 5 for package comparison JB Value 1.5 2.0 ADCLK944 1 Unit °C/W °C/W °C/W °C/W °C/W °C/W ...
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... Differential LVPECL Outputs. 11, 12 Q1, Q1 Differential LVPECL Outputs. 14, 15 Q0, Q0 Differential LVPECL Outputs. EPAD The exposed pad must be connected CLK ADCLK944 T TOP VIEW (Not to Scale) REF CLK NOTES 1. EXPOSED PAD MUST BE CONNECTED Figure 2. Pin Configuration ...
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... CH1 300mV M 250ps 20.0GS/s A CH1 36.0mV Figure 6. LVPECL Differential Output Waveform at 1000 MHz 1.55 +25°C 1.50 1.45 1.40 1.35 1.30 2.2 2.4 2.6 2.8 3.0 3.2 3.4 POWER SUPPLY VOLTAGE (V) and Temperature 1.6 V p-p ID 140 130 120 110 2.5V 100 3. 1.0 1.5 2.0 2.5 DC COMMON-MODE VOLTAGE (V ICM Figure 8. Propagation Delay vs. DC Common-Mode Voltage ADCLK944 IT 5.0ps/pt +85°C –40°C 3.6 3.8 3.0 3.5 – ...
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... CLOCK SOURCE –170 10 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 10. Absolute Phase Noise Measured at 1 GHz with Agilent E5052B –40°C +25°C +85°C 3.300 3.630 − ADCLK944 1M 10M 100M Rev Page www.DataSheet4U.com 300 250 200 150 100 INPUT SLEW RATE (V/ns) Figure 11 ...
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... V p-p. See Figure 18 through Figure 21 for various clock input termination schemes. Output jitter performance is significantly degraded by an input slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate ...
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... When a clamp is required recommended that appropriate external diodes be used. Exposed Metal Paddle The exposed metal paddle on the ADCLK944 package is both an EE electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the V pins ...
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... Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS CONNECT REF PLACE A BYPASS CAPACITOR FROM V GROUND. ALTERNATIVELY, V CONNECTED TOGETHER, GIVING A CLEANE LAY OUT AND A 180° PHASE SHIFT. Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs Rev Page www.DataSheet4U.com ADCLK944 V REF V T 50Ω 50Ω CLK CLK REF V ...
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... ORDERING GUIDE 1 Model Temperature Range ADCLK944BCPZ-R2 −40°C to +85°C ADCLK944BCPZ-R7 −40°C to +85°C ADCLK944BCPZ-WP −40°C to +85°C ADCLK944/PCBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 3.10 0.30 3.00 SQ 0.25 2.90 ...