ADC08231 National Semiconductor, ADC08231 Datasheet - Page 6

• Manufacturer Part Number: ADC08231
• Description: 8-Bit 2 ms Serial I/O A/D Converters with MUX/ Reference/ and Track/Hold
• Manufacturer: National Semiconductor

f
T
t
t
t
t
t
t
C
C
Symbol
Electrical Characteristics
The following specifications apply for V
Boldface limits apply for T
CLK
CA
SELECT
SET-UP
HOLD
pd1
1H
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2 Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits For guaranteed
specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance
characteristics may degrade when the device is not operated under the listed test conditions
Note 3 All voltages are measured with respect to AGND
Note 4 When the input voltage (V
5 mA The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins
Note 5 The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
with suffixes BIN CIN BIJ CIJ BIWM and CIWM T
parts when board mounted follow ADC08231 with BIN and CIN suffixes 120 C W ADC08234 with BIN and CIN suffixes 95 C W ADC08234 with CIMF suffix
167 C W ADC08238 with BIN and CIN suffixes 80 C W ADC08231 with BIWM and CIWM suffixes 140 C W ADC08234 with BIWM and CIWM suffixes 140 C W
ADC08238 with BIWM and CIWM suffixes 91 C W
Note 6 Human body model 100 pF capacitor discharged through a 1 5 k
Note 7 See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or Linear Data Book section ‘‘Surface Mount’’ for other methods of
soldering surface mount devices
Note 8 Typicals are at T
Note 9 Guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 10 Total unadjusted error includes zero full-scale linearity and multiplexer error Total unadjusted error with V
and ADC08238 See Note 16
Note 11 Cannot be tested for the ADC08231
Note 12 For V
for analog input voltages one diode drop below ground or one diode drop greater than V
inputs (e g 5V) can cause an input diode to conduct especially at elevated temperatures This will cause errors for analog inputs near full-scale The specification
allows 50 mV forward bias of either diode this means that as long as the analog V
be correct Exceeding this range on an unselected channel will corrupt the reading of a selected channel Achievement of an absolute 0 V
range will therefore require a minimum supply voltage of 4 950 V
Note 13 Channel leakage current is measured after a single-ended channel is selected and the clock is turned off For off channel leakage current the following
two cases are considered one with the selected channel tied high (5 V
channels is measured two with the selected channel tied low and the off channels tied high total current flow through the off channels is again measured The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured
Note 14 A 40% to 60% duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns The maximum time the clock can be high or low is 100 s
Note 15 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to
allow for comparator response time
Note 16 For the ADC08231 V
reference current (700 A typical 2 mA maximum)
Note 17 Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load
C
IN
OUT
t
0H
t
pd0
IN(
Clock Frequency
Clock Duty Cycle
(Note 14)
Conversion Time (Not Including
MUX Addressing Time)
Acquisition Time
CLK High while CS is High
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK
Rising Edge
CLK Falling Edge to Output
Data Valid (Note 15)
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
Capacitance of Logic Inputs
Capacitance of Logic Outputs
b
) t
V
IN(
J
e
a
)
25 C and represent the most likely parametric norm
the digital code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
REF
Parameter
IN
IN is internally tied to the on chip 2 5V band-gap reference output therefore the supply current is larger because it includes the
) at any pin exceeds the power supplies (V
A
e
T
J
e
CC
T
D
J MAX
MIN
e
(Continued)
e a
(T
J MAX
to T
e
e
125 C For devices with suffix CMJ T
DGND
5 V
b
MAX
DC
T
DC
A
f
C
Data MSB First
Data LSB First
C
(see TRI-STATE Test Circuits)
C
e
over temperature variations initial tolerance and loading
CLK
)
L
L
L
all other limits T
0 V
V
JA
e
e
e
DC
REF
e
DC
or the number given in the Absolute Maximum Ratings whichever is lower For devices
100 pF
10 pF R
100 pF R
) and the remaining off channels tied low (0 V
resistor
4 MHz
IN k
unless otherwise specified
6
Conditions
e a
IN
(AGND or DGND) or V
does not exceed the supply voltage by more than 50 mV the output code will
L
2 5 V
L
CC
e
e
A
supply During testing at low V
10 k
DC
2 k
e
T
and t
J MAX
J
e
J MAX
e
r
25 C
IN l
e
150 C The typical thermal resistances (
JA
t
AV
f
(Note 8)
Typical
and the ambient temperature T
e
CC
10
50
50
5
5
REF
20 ns unless otherwise specified
) the current at that pin should be limited to
e a
CC
DC
levels (e g 4 5V) high level analog
) total current flow through the off
5V only applies to the ADC08234
(Note 9)
Limits
250
200
180
1
40
60
25
20
8
4
2
DC
to 5 V
A
DC
1 f
1 f
MHz (max)
The maximum
kHz (min)
input voltage
% (max)
ns (max)
ns (max)
ns (max)
(Limits)
% (min)
ns (min)
ns (min)
JA
CLK
CLK
Units
s (max)
) of these
pF
pF
ns
ns
(max)
(max)