ADC0820CNED Philips Semiconductors, ADC0820CNED Datasheet - Page 10

• Manufacturer Part Number: ADC0820CNED
• Description: 8-Bit/ high-speed/ mP-compatible A/D converter with track/hold function
• Manufacturer: Philips Semiconductors

Philips Semiconductors Linear Products
before reading the conversion result. INT will typically go Low 800ns
after WR’s rising edge. However, if a shorter conversion time is
desired, the processor need not wait for INT and can exercise a
Read after only 600ns. If this is done, INT will immediately go Low
and data will appear at the outputs.
Stand-Alone (Figure 7)
For stand-alone operation in WR-RD mode, CS and RD can be tied
Low and a conversion can be started with WR. Data will be valid
approximately 800ns following WR’s rising edge.
Other Interface Considerations
In order to maintain conversion accuracy, WR has a maximum width
spec of 50 s. When the MS flash ADC’s sampled data comparators
are in comparison mode (WR is Low), the input capacitors (C,
Figure 5) must hold their charge. Switch leakage can cause errors if
the comparator is left in this phase for too long.
Since the MS flash ADC enters its zeroing phase at the end of a
conversion, a new conversion cannot be started until this phase is
complete. The minimum spec for this time is 500ns (t
2, 3a, and 3b).
ANALOG CONSIDERATIONS
Reference and Input
The two V
the zero- to full-scale input range of the A/D converter. This allows
the designer to easily vary the span of the analog input since this
range will be equivalent to the voltage difference between V
and V
-V
increased (i.e., if V
arrangement also facilitates ratiometric operation and, in many
cases, the chip power supply can be used for transducer power as
well as the V
August 31, 1994
REF
8-Bit, high-speed, P-compatible A/D converter with
track/hold function
RD LOW
DB0–DB7
CS LOW
IN
(-)) to less than 5V, the sensitivity of the converter can be
(-). By reducing V
WR
INT
REF
REF
Figure 7. WR-RD Mode (Pin 7 is High)
inputs of the ADC0820 are fully differential and define
source.
REF
Stand-Alone Operation
=2V, then 1 LSB=7.8mV). The input/reference
REF
(V
REF
=V
REF
(+)
P
in Figures 1,
IN
(+)
577
This reference flexibility lets the input span not only be varied, but
also offset from zero. The voltage at V
which produces a digital output of all zeroes. Though V
differential, the reference design affords nearly differential-input
capability for most measurement applications. Figure 9 shows some
of the configurations that are possible.
Input Current
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently than in
conventional devices. The A/D’s sampled data comparators take
varying amounts of input current depending on which cycle the
conversion is in.
The equivalent input circuit of the ADC0820 is shown in Figure 10a.
When a conversion starts (WR Low, WR-RD mode), all input
switches close, connecting V
two 4-bit flash circuits are not both in their compare cycle at the
same time, V
because the MS flash converter is connected to the input during its
compare interval and the LS flash is connected to the input during its
zeroing phase. In other words, the LS ADC uses V
zero-phase input.
The input capacitors must charge to the input voltage through the on
resistance of the analog switches (about 5k to 10k ). In addition,
about 12pF of input stray capacitance must also be charged. For
large source resistances, the analog input can be modeled as an
RC network as shown in Figure 10b. As R
longer for the input capacitance to charge.
In RD mode, the input switches are closed for approximately 800ns
at the start of the conversion. In WR-RD mode, the time that the
switches are closed to allow this charging is the time that WR is
Low. Since other factors force this time to be at least 600ns, input
time constants of 100ns can be accommodated without special
consideration. Typical total input capacitance values of 45pF allow
R
settle.
Input Filtering
It should be made clear that transients in the analog input signal,
caused by charging current flowing into V
A/D’s performance in most cases. In effect, the ADC0820 does not
“look” at the input when these transients occur. The comparators’
outputs are not latched while WR is Low, so at least 600ns will be
provided to charge the ADC’s input capacitance. It is
S
to be 1.5k without lengthening WR to give V
IN
still sees all input capacitors at once. This is
IN
to 31 1pF capacitors. Although the
REF
IN
(-) sets the input level
S
, will not degrade the
increases, it will take
Product specification
ADC0820
IN
IN
more time to
as its
IN
is not itself