ADC-0803 Harris, ADC-0803 Datasheet - Page 11

• Manufacturer Part Number: ADC-0803
• Description: (ADC0802 - ADC0804) 8-Bit/ Microprocessor- Compatible/ A/D Converters
• Manufacturer: Harris

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Reference Accuracy Requirements
The converter can be operated in a pseudo-ratiometric mode
or an absolute mode. In ratiometric converter applications,
the magnitude of the reference voltage is a factor in both the
output of the source transducer and the output of the A/D
converter and therefore cancels out in the final digital output
code. In absolute conversion applicatIons, both the initial
value and the temperature stability of the reference voltage
are important accuracy factors in the operation of the A/D
converter. For V
errors of 10mV will cause conversion errors of 1 LSB due
to the gain of 2 of the V
tions, the initial value and the stability of the V
voltage become even more important. For example, if the
span is reduced to 2.5V, the analog input LSB voltage value
is correspondingly reduced from 20mV (5V span) to 10mV
and 1 LSB at the V
seen, this reduces the allowed initial tolerance of the refer-
ence voltage and requires correspondingly less absolute
change with temperature variations. Note that spans smaller
than 2.5V place even tighter requirements on the initial accu-
racy and stability of the reference source.
In general, the reference voltage will require an initial
adjustment. Errors due to an improper value of reference
voltage appear as full scale errors in the A/D transfer func-
tion. IC voltage regulators may be used for references if the
ambient temperature changes are not excessive.
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by bias-
ing the A/D V
section). This utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V
positive voltage to the V
between the actual DC input voltage which is necessary to
just cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal
V
REF
V
IN
FIGURE 15. HANDLING 5V ANALOG INPUT RANGE
/2 = 2.500V).
5V
IN(-)
R
REF
IN(-)
input at this V
/2 voltages of 2.5V nominal value, initial
REF
input and applying a small magnitude
R
REF
IN(+)
/2 input becomes 5mV. As can be
1
6
7
/
2
/2 input. In reduced span applica-
input. Zero error is the difference
LSB value (
V
V
ADC0802-
ADC0804
IN(+)
IN(-)
lN(MlN)
V+
lN(MlN)
value (see Applications
20
1
ADC0802, ADC0803, ADC0804
/
2
LSB = 9.8mV for
, is not ground, a
+
10 F
REF
/2 input
(V
5V
REF
)
6-15
Full Scale Adjust
The full scale adjustment can be made by applying a
differential input voltage which is 1
desired analog full scale voltage range and then adjusting
the magnitude of the V
code which is just changing from 1111 1110 to 1111 1111.
When offsetting the zero and using a span-adjusted V
voltage, the full scale adjustment is made by inputting V
to the V
V
where:
V
and
V
(Both are ground referenced.)
Clocking Option
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
Heavy capacitive or DC loading of the CLK R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50pF, such as driving up to 7 A/D converter
clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the CLK R pin (do not use a standard TTL buffer).
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in progress is not completed. The data from the
previous conversion remain in this latch.
Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-
up cycle to insure circuit operation. See Figure 17 for details.
V
IN(+)
MAX
MIN
IN +
CLK IN
f
= the low end (the offset zero) of the analog range.
= the high end of the analog input range,
input which is given by:
SADJ
IN(-)
R
C
FIGURE 16. SELF-CLOCKING THE A/D
=
input of the A/D and applying a voltage to the
CLK R
V
MAX
–
1.5
REF
-----------------------------------------
19
/2 input (pin 9) for a digital output
V
4
MAX
ADC0802-
ADC0804
256
–
V
1
MIN
/
2
CLK
LSB down from the
,
f
R
CLK
10k
1.1 RC
1
REF
MlN
/2