MPC9448 Motorola, MPC9448 Datasheet - Page 5

• Manufacturer Part Number: MPC9448
• Description: 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
• Manufacturer: Motorola

a. AC characteristics apply for parallel output termination of 50Ω to V
b. V
c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
d. Output pulse skew is the absolute difference of the propagation delay times: | t
TIMING SOLUTIONS
Table 8. AC CHARACTERISTICS (V
Symbol
t
t
t
t
V
t
PLZ, HZ
t
PLH/HL
PLH/HL
PZL, LZ
and the input swing lies within the V
pulse width, output duty cycle and maximum frequency specifications.
P, REF
t
t
sk(PP)
DC
f
V
SK(p)
CMR
sk(O)
MAX
t
t
f
CMR
r
r
t
t
ref
, t
, t
PP
S
H
Q
f
f
b
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Setup time
Hold time
Output-to-output Skew
Device-to-device Skew
Output pulse skew
Output Duty Cycle
Output Rise/Fall Time
d
Characteristics
PP
Freescale Semiconductor, Inc.
f
(AC) specification. Violation of V
Q
f
CC
Q
< 350 MHz and using CCLK
For More Information On This Product,
<200 MHz and using PCLK
= 2.5V ±5%, T
PCLK or CCLK to any Q
CCLK to CLK_STOP
PCLK to CLK_STOP
CCLK to CLK_STOP
PCLK to CLK_STOP
Go to: www.freescale.com
CCLK to any Q
PCLK to any Q
Using CCLK
Using PCLK
A
= --40°C to +85°C)
PCLK
PCLK
TT
5
.
CMR
Min
400
1.2
1.4
1.5
1.7
0.0
0.0
1.0
1.5
0.1
45
45
or V
0
0
pLH
PP
a
- t
impacts t
pHL
|.
Typ
50
50
PLH/HL
and t
V
1000
CC
Max
350
350
1.0
150
200
300
4.2
4.4
2.7
1.0
55
55
11
11
-0.8
SK(PP)
c
.
MHz
MHz
Unit
mV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
ps
ns
%
%
V
LVPECL
LVPECL
0.8 to 2.0V
DC
0.6 to 1.8V
MPC9448
Condition
REF
MOTOROLA
CMR
= 50%
range