MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 25

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Note 1:
Note 2:
*
B6-B5
B7-B2
BIT
BIT
B1*
B0*
B7
B4
B3
B2
B1
B0
These two bits can be used along with status bits IS0 and IS1 to distinguish between states F6/F8 and F4/F5 of the device’s state machine
in TE mode. Please refer to “State Machine” section of Application Note MSAN-141 for further details.
Bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250
The Status Register is updated internally once every ST-BUS frame. Therefore, more than one read access per frame will
consecutive ones are received.
return the same value.
Sync/BA
RxMFR
IS0-IS1
Priority
DCack
NAME
NAME
INFO1
INFO0
HALF
M/S
NA
This bit is set if the device has achieved frame synchronization while the activation request
is asserted (DR = 0 and AR = 1). If there is a deactivation request or that AR is low ( DR =
1 or AR = 0), this pin indicates the presence of bus activity
reception of INFO frames (INFO2 or INFO4).
Binary encoded state sequence.
This bit respresents the state of the received M/S-bit. M when HALF=0 and S when
HALF=1
The state of this bit identifies which half of the S-Bus frame is currently being output on the
ST-BUS.
A ’1’ when HALF=0 indicates that the multiframe pattern on Fa and N has been detected.
The status of this bit indicates the internal priority of the device within the designated
priority class. If 1, then it has high priority within the priority class designated in B4 of
control register. If 0, then it has low priority within the priority class designated in B4 of
control register.
A ’1’ indicates that the device has gained access to the D-channel and has transmitted an
opening flag. This bit is reset to ‘0’ when the closing flag of the last packet in the TxFIFO is
transmitted and the internal priority is reduced from high to low. A collision during
transmission will also reset this bit back to ‘0’.
Not available.
In TE mode, this bit is set to ‘1’ only when the device is transmitting INFO1.
Not available in NT mode.
In NT or TE mode, this bit is set to ‘1’ only when the device is transmitting INFO0.
Table 18. TE Mode Status Register
Table 19. Master Status Register (Read Add. 10010
IS0 - IS1
0 -
0 -
1 -
1 -
0
1
0
1
- deactivated
- synchronized
- activation request
- activated
DESCRIPTION
DESCRIPTION
(2)
(Read Add. 01001
(1)
.
B
)
A bus activity identifies the
B
)
µ
s. It is reset when 128
MT8930C
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