MT8920 Zarlink Semiconductor, MT8920 Datasheet - Page 20
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MT8920
Manufacturer Part Number
MT8920
Description
32 Channels TDM (ST-BUS) to Parallel Bus Access Circuit
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT8920.pdf
(27 pages)
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MT8920B
20
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
testing.
AC Electrical Characteristics
((V
10 Read Data Hold Time
12 Write Data Hold Time
13 C4i Transition to STCH, DCS Trans.
14 STCH Pulse Width
15 DCS Pulse Width
11 Write Data Setup Time
1
2
3
4
5
6
7
8
9
CC
=5.0V
CS to OE, WE, Address Enabled
C4i Low to Address Change
CS to OE, WE, Address Disabled
C4i Low to Output Enable Low
C4i Low to Output Enable High
OE, WE, Pulse Width
C4i Low to Write Enable Low
C4i Low to Write Enable High
Read Data Valid from OE
±
5%,TA=-40 to 85
A4 - A0
D7 - D0
WE
C4i
OE
CS
Characteristics
t
°
ACS
C, V
°
t
ZR
DD
C)
BIT 7 (BIT 3)
=5V,t
CLK
=244ns, t
†
t
t
OED
N + 1
RST
- Mode 3 Timing (see Fig.17, 18 and 19)
Figure 17 - Mode 3 Timing Diagram
CH
t
ENPW
t
t
t
=t
Sym
ENPW
t
t
SCPW
CSPW
t
t
t
t
t
t
t
t
WED
WEH
WST
t
ACS
t
OED
RHT
RST
WHT
STC
OEH
CL
ZR
RZ
BIT 6 (BIT 2)
DATA IN
=122ns and are for design aid only: not guaranteed and not subject to production
Min
70
70
0
CHANNEL N
t
OEH
2*t
1830
1830
Typ
100
100
t
50
RHT
CLK
‡
BIT 5 (BIT 1)
(2*t
t
WST
Max
110
120
-60
50
75
75
75
75
t
CLK
WED
)
Units
N - 1
DATA OUT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ENPW
BIT 4 (BIT 0)
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
Load A, C
t
WEH
Test Conditions
t
WHT
t
L
L
L
L
L
L
L
L
L
L
L
L
L
RZ
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 130pF, R
= 70pF, R
= 70pF, R
= 70pF, R
Data Sheet
L
L
L
L
L
L
L
L
L
L
L
L
L
= 1.22KΩ
= 1.22KΩ
= 1.22KΩ
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω
= 740Ω