MPC8260A Motorola, MPC8260A Datasheet - Page 18

• Manufacturer Part Number: MPC8260A
• Description: Micro Processor
• Manufacturer: Motorola

Electrical and Thermal Characteristics
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 10 shows signal behavior in MEMC mode.
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DATA bus, ECC, and PARITY mode input signals
Memory controller signals
1:2, 1:3, 1:4, 1:5, 1:6
PLL Clock Ratio
Generally, all MPC826xA bus and system output signals are driven from
the rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
1:2.5
1:3.5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 13. Tick Spacing for Memory Controller Signals
CLKin
V_CLK
MPC826xA (HiP4) Family Hardware Specifications
DP mode output signal
Figure 10. MEMC Mode Diagram
1/4 CLKin
3/10 CLKin
4/14 CLKin
DP mode input signal
Figure 9. Parity Mode Diagram
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
NOTE
CLKin
1/2 CLKin
1/2 CLKin
1/2 CLKin
sp34/sp30
sp14
sp13
T3
3/4 CLKin
8/10 CLKin
11/14 CLKin
sp10
sp10
T4
sp33b/sp30
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