MT93L16AQ Zarlink Semiconductor, MT93L16AQ Datasheet
MT93L16AQ
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MT93L16AQ Summary of contents
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... Rout /A-Law Limiter VSS VDD RESET Low-Voltage Acoustic Echo Canceller DS5068 MT93L16AQ • AGC on speaker path • Handles acoustic echo return loss and 0dB line ERL • Transparent data transfer and mute options • 20 MHz master clock operation • ...
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MT93L16 Pin Description Pin # Name 1 ENA1 SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input) . This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present ...
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Preliminary Information Pin Description (continued) Pin # Name 14 RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a low-power stand-by mode. 15 Connect (Output). These pins should be left ...
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MT93L16 Functional Description The MT93L16 device contains two echo cancellers, as well as the many control functions necessary to operate the echo cancellers. One canceller is for acoustic speaker to microphone echo, and one for line echo cancellation. The MT93L16 ...
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Preliminary Information 4 Howling Detector (HWLD) (4. Patent Pending) The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the ...
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MT93L16 Power Down / Reset Holding the RESET pin at logic low will keep the MT93L16 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated. The user ...
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Preliminary Information C4i start of frame (stbus & GCI) F0i (ST-BUS) 0 F0i (GCI) PORT1 Rin Sout PORT2 Sin Rout outputs = High impedance inputs = don’t care In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI ...
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MT93L16 C4i start of frame (stbus & GCI) F0i (stbus) F0i (GCI) Rin PORT1 Sout Sin ...
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Preliminary Information BCLK PORT1 ENA1 Rin Sout PORT2 ENA2 Sin Rout outputs = High impedance inputs = don’t care Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can ...
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MT93L16 Microport The serial microport provides access to all MT93L16 internal read and write registers, plus write-only access to the bootloadable program RAM (see next section for bootload description.) This microport is compatible with Intel MCS-51 (mode 0), Motorola SPI ...
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Preliminary Information FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM) R/W W BRC Register (= Bits ...
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Preliminary Information MT93L16 12 ...
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MT93L16 COMMAND/ADDRESS DATA 1 R SCLK CS This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16. The MT93L16: latches receive data on the ...
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Preliminary Information Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Input Voltage 3 Output Voltage Swing 4 Continuous Current on any digital pin 5 Storage Temperature 6 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation ...
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MT93L16 AC Electrical Characteristics otherwise stated Characteristics 1 MCLK Frequency 2 BCLK/C4i Clock High 3 BCLK/C4i Clock Low 4 BCLK/C4i Period 5 SSI Enable Strobe to Data Delay (first bit) 6 SSI Data Output Delay (excluding first bit) 7 SSI ...
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Preliminary Information AC Electrical Characteristics Characteristics 1 Input Data Setup 2 Input Data Hold 3 Output Data Delay 4 Serial Clock Period 5 SCLK Pulse Width High 6 SCLK Pulse Width Low 7 CS Setup-Intel 8 CS Setup-Motorola 9 CS ...
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MT93L16 Bit 7 (O) Sout/Rout t DSD V H (I) C4i F0iS F0iH V H (I) F0i DSS start of frame V H (I) Rin/Sin (O) Sout/Rout t DSD V ...
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Preliminary Information (I,O) DATA1 t IDS V H (I) SCLK CSSI Notes: O. CMOS output I. CMOS input (5V tolerant) (see Table 8 for symbol definitions (I) DATA2 ...
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MT93L16 Register Summary Address: 00h R Power Up LIMIT MUTE_R Reset 00h MSB RESET When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to’0’ when reset is complete. ...
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Preliminary Information Address: Acoustic Echo Canceller Status Register 22h Read 7 6 Power Up - ACMUND Reset 00h MSB NBS When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not ...
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MT93L16 Address: 16h Read 7 6 Power Up RIPD RIPD 7 Reset 00h MSB RIPD 0 RIPD 1 These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see Figure ...
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Preliminary Information Address: Receive (Rout) Peak Detect Register 3Ah Read 7 6 Power Up ROPD ROPD 7 Reset 00h MSB ROPD 0 ROPD 1 These peak detector registers allow the user to monitor the receive out signal (Rout) peak level ...
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MT93L16 Address: Send ERROR Peak Detect Register 38h Read 7 6 Power Up SEPD SEPD 7 Reset 00h MSB SEPD 0 SEPD 1 These peak detector registers allow the user to monitor the error signal peak level in the send ...
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Preliminary Information Address: Acoustic Echo Canceller Adaptation Speed Register 3Ch R Power Up A_AS A_AS 7 Reset 00h MSB A_AS 0 This register allows the user to program control the adaptation speed of the Acoustic Echo Canceller. This ...
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MT93L16 Address: 24h R Power Reset 80h MSB - - - RESERVED - - - - L This bit is used in conjunction with Rout Limiter Register 2. (See description below.) 0 Address: 25h ...
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Preliminary Information Address: 03h Read 7 6 Power Up FRC FRC 2 Reset 00h MSB - - RESERVED - - FRC 0 FRC 1 Revision code of the firmware program currently being run (default=rom=00). FRC 2 Address: 3fh R / ...
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MT93L16 Pin # Notes: 1. Lead Coplanitary should 0.10mm (.004") max 2. Package surface finishing (2.1) Top Matte: (Charmilles #18-30) (2.2) All Sides: (Charmilles #18-30) (2.3) Bottom Matte: (Charmilles #18-30) 3. All ...
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Preliminary Information Notes: MT93L16 28 ...
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