MPC5534 Frescale, MPC5534 Datasheet - Page 23

• Manufacturer Part Number: MPC5534
• Description: Microcontroller
• Manufacturer: Frescale

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5.2
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and
five slave ports.
The crossbar allows for concurrent transactions to occur from any master port to any slave port. It is
possible for all master ports and slave ports to be in use at the same time as a result of independent master
requests. If a slave port is simultaneously requested by more than one master port, arbitration logic will
select the higher priority master and grant it ownership of the slave port. All other masters requesting that
slave port will be stalled until the higher priority master completes its transactions. By default, requesting
masters will be treated with equal priority and will be granted access to a slave port in round-robin fashion,
based upon the ID of the last master to be granted access.
5.3
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data movements via 32 programmable channels, with minimal intervention from the
host processor. The hardware micro architecture includes a DMA engine which performs source and
destination address calculations, and the actual data movement operations, along with an SRAM-based
memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized
to minimize the overall block size.
5.4
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests,
suitable for statically scheduled hard real-time systems. The INTC allows interrupt request servicing from
up to 210 interrupt sources.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
Freescale Semiconductor
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•
Four master ports:
— Core CPU - Instruction
— Core CPU - Data
— eDMA
— EBI
Five slave ports
— Flash (64-bit data access)
— EBI (64-bit data access)
— SRAM (64-bit data access)
— Peripheral Bridge A (32-bit data access)
— Peripheral Bridge B (32-bit data access)
Crossbar switch (XBAR)
Enhanced direct memory access (eDMA) controller
Interrupt Controller (INTC)
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MPC5534 Microcontroller Product Brief, Rev. 0.0
Detailed Features
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