MT9125AE Zarlink Semiconductor, MT9125AE Datasheet - Page 2

• Manufacturer Part Number: MT9125AE
• Description: MT9125 - Dual Adpcm Transcoder
• Manufacturer: Zarlink Semiconductor

MT9125
8-74
Pin Description
DIP
1
2
3
4
5
Pin #
PLCC
2
3
4
5
6
28 PIN PLCC
24 PIN PDIP
MCLK
Name
DSTo
DSTi
C2o
F0i
Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be
provided during both ST-BUS and SSI modes of operation. This is a TTL level input.
In ST-BUS mode the MCLK input (also known as C4i in ST-BUS terms) is derived from the
synchronous 4.096 MHz clock available from the layer 1 transceiver device. The C4i clock,
input to MCLK, is used in this mode as both the internal master clock and for deriving the
C2o output clock and EN1/EN2 output enable strobes.
In SSI mode a 4.096 MHz master clock must be derived from an external source. This
master clock may be asynchronous relative to the 8 kHz frame reference.
Frame alignment input pulse for ST-BUS interface operation. This input should be tied low
if ST-BUS operation is not required.
This is a TTL level input.
2.048MHz Clock output for ST-BUS applications. This clock is MCLK divided by 2 and
inverted. The C2o output activity state is governed by the F0i input pin condition.
Serial PCM octet output stream. Refer to the serial timing diagram of Figure 12.
Serial PCM octet input data stream. Refer to the serial timing diagram of Figure 12.
This is a TTL level input.
Active F0i strobe
F0i input
V
V
SS
DD
BCLK
ENB2
ENB1
DSTo
DSTi
Figure 2 - Pin Connections
VSS
NC
MCLK
BCLK
ENB2
ENB1
DSTo
DSTi
MS1
MS2
MS3
VSS
C2o
F0i
C2o output
disabled (SSI mode automatically activated)
enabled
enabled and aligned to F0i due to C4i input at MCLK
5
6
7
8
9
10
11
10
11
12
1
2
3
4
5
6
7
8
9
Description
24
23
22
21
20
19
18
17
16
15
14
13
25
24
23
22
21
20
19
ENS
EN2
EN1
ADPCMo
ADPCMi
ENA
VDD
IC
PWRDN
FORMAT
A/
MS4
ADPCMo
ADPCMi
ENA
VDD
NC
IC
PWRDN
Preliminary Information