MT9125 Zarlink Semiconductor, MT9125 Datasheet - Page 9

• Manufacturer Part Number: MT9125
• Description: Dual Adpcm Transcoder
• Manufacturer: Zarlink Semiconductor

MT9125
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at
BCLK. BCLK must be eight periods in duration and
synchronous with the 8 kHz frame input at ENB1.
Data is sampled at DSTi and at ADPCMi concurrent
with the falling edge of BCLK. Data is available at
DSTo and ADPCMo concurrent with the rising edge
of BCLK. BCLK may be any rate between 128 kHz
and 2.048 MHz. Refer to Figures 12 and 13.
For ST-BUS operation BCLK is ignored and the bit
rate is internally set to 2.048 MHz.
PCM Law Control (A/ , FORMAT)
The PCM companding/coding law invoked by the
transcoder is controlled via the A/ and FORMAT
pins. CCITT G.711 companding curves,
A-Law, are
Law; 1=A-Law). Per sample, digital code assignment
can conform to CCITT G.711 (when FORMAT=1) or
to Sign-Magnitude coding (when FORMAT=0). Table
1 illustrates these choices.
8-80
DSTi
ADPCMo
ENA
ENB1 or
EN1
MS1/3
MS2/4
determined
PCM Byte "X" latched into device
1,1=32 kb/s
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames. See Figure 15 for detailed ENB1/EN1 timing.
during frame n-1
frame n-1
Figure 6 - Pipelining for Dynamic 32/24 kb/s Operation
by the
A/
pin (0= -
-Law and
1,0=24 kb/s
PCM Byte "X" processed according
to MSn input states latched during
Processing Delay through the Device
One 8 kHz frame is required for serial loading of the
input buffers, and one frame is required for
processing, for a total of two frame delays through
the device. All internal input/output PCM and
ADPCM shift registers are parallel loaded through
secondary buffers on an internal frame pulse. The
device derives its internal frame reference from the
F0i, ENB1 and ENB2 pins in the following manner. If
a valid ST-BUS frame pulse is present at the F0i pin
the transcoder will assume ST-BUS operation and
will use this input as the frame reference. In this
frame n
frame n
PCM Code
+ Full Scale
- Full Scale
+ Zero
- Zero
A/ = 0 or 1
Magnitude
1111 1111
1000 0000
0000 0000
0111 1111
Sign-
0
Preliminary Information
ADPCM Word "X" output from
1,1=32 kb/s
Table 1
device during frame n+1
FORMAT
(A/ = 0)
1000 0000
1111 1111
0111 1111
0000 0000
frame n+1
CCITT (G.711)
1
(A/ = 1)
1010 1010
1101 0101
0101 0101
0010 1010