MT9123AE Zarlink Semiconductor, MT9123AE Datasheet - Page 9

• Manufacturer Part Number: MT9123AE
• Description: Description = Dual Voice Echo CANceller ( Itu-t G165 Compliant) ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Controller Mode
In Control Register 1, the Normal configuration can
be programmed by setting both BBM and Extended-
Delay bits to 0. Back-to-Back configuration can be
programmed by setting the BBM bit to 1 and
Extended-Delay
configuration can be programmed by setting the
Extended-Delay bit to 1 and BBM bit to 0. Both BBM
and Extended-Delay bits in Control Register 1 can
not be set to 1 at the same time.
PCM Data I/O
The PCM data transfer for the MT9123 is provided
through two PCM ports. PORT1 consists of Rin and
Sout pins while PORT2 consists of Sin and Rout Pins.
The Data is transferred through these ports
according to either ST-BUS or SSI conventions. The
device determines the mode of operation by
monitoring the signal applied to the F0i pin. When a
valid ST-BUS frame pulse is applied to the F0i pin,
the MT9123 will assume ST-BUS operation. If F0i is
tied continuously to Vss the MT9123 will assume SSI
operation.
ST-BUS Operation
The ST-BUS PCM interface conforms to Zarlink’s
ST-BUS standard and it is used to transport 8 bit
companded PCM data (using one timeslot) or 16 bit
2’s complement linear PCM data (using two
timeslots). Pins ENA1 and ENB1 select timeslots on
PORT1 while pins ENA2 and ENB2 select timeslots
on PORT2. See Table 4 and Figures 5 to 8.
Table 3 - Configuration in Controllerless Mode
CONFIG1
0
0
1
1
CONFIG2
bit
0
1
0
1
to
(selects Controller Mode)
0.
Extended Delay Mode
Back-to-Back Mode
CONFIGURATION
Normal Mode
Extended-Delay
Note that if the device is in back-to-back or extended
delay configurations, the second timeslot in any ST-
BUS Mode contains undefined data. This means that
the following timeslots contain undefined data:
timeslot 1 in ST-BUS Mode 1; timeslot 3 in ST-BUS
Modes 2 & 3 and timeslots 2 and 3 in ST-BUS Mode
4.
SSI Operation
The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and four enable pins
(ENA1,ENB1, ENA2 and ENB2) to provide strobes
for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic
detection of the data type (8 bit companded or 16 bit
2’s complement linear) is accomplished internally.
The data type cannot change dynamically from one
frame to the next.
In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 9). The other enable strobes (ENB1, ENA2
and ENB2) are used for parsing input/output data
and they must pulse within 125 microseconds of the
rising edge of ENA1. If they are unused, they must
be tied to Vss.
In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2’s complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).
ENB1 ENA1
Rin/Sout
Enable Pins
PORT1
0
0
1
1
0
1
0
1
Mode 1. 8 bit companded PCM I/O on
timeslots 0 & 1.
Mode 2. 8 bit companded PCM I/O on
timeslots 2 & 3.
Mode 3. 8 bit companded PCM I/O on
timeslots 2 & 3. Includes D & C chan-
nel bypass in timeslots 0 & 1.
Mode 4. 16 bit 2’s complement linear
PCM I/O on timeslots 0 - 3.
Table 4 - ST-BUS Mode Select
ST-BUS Mode
Selection
MT9123
ENB2
Enable Pins
Sin/Rout
PORT2
0
0
1
1
ENA2
0
1
0
1
9