HY29DL163 Hynix Semiconductor, HY29DL163 Datasheet - Page 19

• Manufacturer Part Number: HY29DL163
• Description: (HY29DL162 / HY29DL163) Simultaneous Read/Write Flash Memory
• Manufacturer: Hynix Semiconductor

When the Automatic Erase algorithm is complete,
the device returns to the reading array data mode.
Several methods are provided to allow the host to
determine the status of the erase operation, as
described in the Write Operation Status section.
Figure 5 illustrates the chip erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by a set-up com-
r1.3/June 01
(See Write Operation Status
CHIP ERASE COMPLETE
I s s u e N O R M A L P R O G R A M
C o m m a n d S e q u e n c e
Issue CHIP ERASE
Check Erase Status
Figure 5. Chip Erase Procedure
Section)
C o m m a n d
START
Normal Exit
Figure 4. Normal and Unlock Bypass Programming Procedures
DQ[5] Error Exit
N O
N O
Setup Next Address/Data for
I s s u e U N L O C K B Y P A S S
I s s u e U N L O C K B Y P A S S
ERROR RECOVERY
P R O G R A M C o m m a n d
Program Operation
C o m m a n d t o B a n k
Bank in Unlock
Bypass Mode?
P r o g r a m m i n g ?
Enable Fast
GO TO
S T A R T
Y E S
Y E S
mand, two additional unlock cycles and then the
Sector Erase command, which specifies which
sector is to be erased. This sequence invokes
the Automatic Erase algorithm that automatically
preprograms (if necessary) and verifies the speci-
fied sector for an all zero data pattern prior to elec-
trical erase. The host system is not required to
provide any controls or timings during these op-
erations.
After the sector erase data cycle (the sixth cycle)
of the command sequence is issued, a sector
erase time-out of 50 µs (min) begins, measured
from the rising edge of the final WE# pulse in the
command sequence. During this time, an addi-
tional sector address and sector erase data cycle
may be written into an internal sector erase buffer.
This buffer may be loaded in any sequence, and
the number of sectors designated for erasure may
be from one sector to all sectors. The only re-
striction is that the time between these additional
cycles must be less than 50 µs, otherwise era-
sure may begin before the last address and com-
mand are accepted. To ensure that all commands
are accepted, it is recommended that host pro-
cessor interrupts be disabled during the time that
N O
N O
(See Write Operation Status
Check Programming Status
R E S E T C o m m a n d t o B a n k
I s s u e U N L O C K B Y P A S S
PROGRAMMING
Last Word/Byte
Bank in Unlock
Bypass Mode?
C O M P L E T E
Section)
D o n e ?
Y E S
Programming Verified
Y E S
HY29DL162/HY29DL163
DQ[5] Error Exit
RECOVERY PROCEDURE
GO TO ERROR
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