MT1020A Zarlink Semiconductor, MT1020A Datasheet - Page 2

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MT1020A

Manufacturer Part Number
MT1020A
Description
Manufacturer
Zarlink Semiconductor
Datasheet
MT1020A
2
Memory/Peripheral Interface
SADD[18:0]
SDATA[15:0]
NSCS[1:0]
NSCS[3]
NSWE[1:0]
NSOE
NSUB
SWAIT
UART1
U1RXD
U1TXD
U1RTS
U1CTS
Host Interfaces
HST_UART_RXD
Signal Name
Preliminary Information
(see notes)
C6: B1: C7:
D6: C3: C2:
A8: A9: C8:
C9: F7: B9:
D4: D7: F9:
D8: B8: E7:
H4: H9: J1:
K2: K4: L3:
J2: J4: K1:
G10: G8:
G9: H10:
D3: E4:
B6: E6
K3: L2
F10
Pin
B7
A1
B5
D2
E3
E2
C5
L4
F3
F4
Table 1 - Pin Descriptions
I/O Type
Figure 2 - Pin Connections
I/O(hd)
O(hd)
O(hd)
O(hd)
O(hd)
O(hd)
I(pd)
I(hd)
I(hd)
I(hd)
O
O
O
Qty
19
16
2
1
2
1
1
1
1
1
1
1
1
System Address
System Data Bus
Active low System Chip Select 1 and 0
Active low System Chip Select 3
Active low System Write Enable 1 and 0
Active low System output enable
Active low System Upper Byte (for 16-bit
RAM)(SADD[0] = lower byte)
System Wait. Extended MPC access
UART1 Receive Data
UART1 Transmit Data
UART1 Ready to Send (active low
UART1 Clear to Send (active low
Serial Host Interface Receive Data
Description
1
)
1
)

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