AT91SAM9261S ATMEL Corporation, AT91SAM9261S Datasheet - Page 21
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AT91SAM9261S
Manufacturer Part Number
AT91SAM9261S
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9261S.pdf
(39 pages)
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Part Number:
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9.2
9.3
9.4
9.5
6242DS–ATARM–06-Jan-09
Reset Controller
Shutdown Controller
General-purpose Backup Registers
Clock Generator
Figure 9-2.
• Based on two Power-on-Reset cells
• Status of the last reset
• Controls the internal resets and the NRST pin output
• Shutdown and Wake-up logic:
• Four 32-bit general-purpose backup registers
• Embeds the Low-power 32768 Hz Slow Clock Oscillator
• Embeds the Main Oscillator
• Embeds Two PLLs
• Provides SLCK, MAINCK, PLLACK and PLLBCK.
– Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
– Provides the permanent Slow Clock to the system
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
– Outputs 80 to 240 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz minimum input frequency
Clock Generator Block Diagram
XOUT32
PLLRCA
PLLRCB
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Controller
Oscillator
Oscillator
PLL and
Divider A
PLL and
Divider B
Status
Power
Main
Control
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
AT91SAM9261S
21