AT91R40008 ATMEL Corporation, AT91R40008 Datasheet - Page 9

• Manufacturer Part Number: AT91R40008
• Description: AT91 ARM Thumb Microcontroller
• Manufacturer: ATMEL Corporation

JTAG/ICE Debug
Memory Controller
Internal Memories
Boot Mode Select
1732DS–ATARM–03/04
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-
fies the microcontroller. This is not fully IEEE1149.1 compliant.
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
•
•
•
In any of these address spaces, the ARM7TDMI operates in Little-endian mode only.
The AT91R40008 microcontroller integrates 256K bytes of internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-
bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching
Thumb or ARM instructions is supported and internal memory can store twice as many
Thumb instructions as ARM ones.
The SRAM is mapped at address 0x0 (after the Remap command), allowing
ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the
microcontroller performance and minimizes the system power consumption. The 32-bit
bus increases the effectiveness of the use of the ARM instruction set and the ability of
processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI
advanced performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an
extra dimension to the AT91R40008.
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory (see Table 3).
The BMS pin is multiplexed with the I/O line P24, which can be programmed after reset
like any standard PIO line.
Table 3. Boot Mode Select
Internal memories in the four lowest megabytes
Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
Internal peripherals in the four highest megabytes
BMS
1
0
Boot Memory
External 8-bit memory on NCS0
External 16-bit memory on NCS0
AT91R40008 - Summary
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