AT90LS4434-4AI ATMEL Corporation, AT90LS4434-4AI Datasheet - Page 5

• Manufacturer Part Number: AT90LS4434-4AI
• Description: 8-Bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 3
shows the AT90S4434/8535 AVR Enhanced RISC micro-
controller architecture.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept
Figure 4. Memory Maps
Program Memory
Program Flash
(2K/4K x 16)
$000
$7FF/$FFF
Working Registers
32 Gen. Purpose
64 I/O Registers
Internal SRAM
Data Memory
(256/512 x 8)
enables instructions to be executed in every clock cycle.
The program memory is in-system downloadable Flash
memory.
With the relative jump and call instructions, the whole
2K/4K address space is directly accessed. Most AVR
instructions have a single 16-bit word format. Every pro-
gram memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 9-bit stack pointer SP is read/write
accessible in the I/O space.
The 256/512 bytes data SRAM can be easily accessed
through the five different addressing modes supported in
the AVR architecture.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
$015F/$025F
$0000
$001F
$0020
$005F
$0060
(256/512 x 8)
Data Memory
EEPROM
$0000
$1F/$FF
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