AD8309 Analog Devices, AD8309 Datasheet - Page 17

• Manufacturer Part Number: AD8309
• Description: 5 - 500 Mhz, 100 DB Demodulating Logarithmic Amplifier With Limiter Output
• Manufacturer: Analog Devices

Slope
mV/dB dBV
40
50
40
50
Setting the Limiter Output Level
The limiter output is a pair of differential currents of magni-
tude, I
These are converted to equal-amplitude voltages by supply-
referenced load resistors, R
set by R
ground depending on the application, the resulting voltage may
be used in a fully balanced or unbalanced manner. It is good
practice to retain the both resistors, whichever output mode is
used. The unbalanced, or single sided mode, is more inclined to
result in instabilities caused by the very high gain of the signal
path. If the limiter output is not needed, LMDR should be left
open with LMHI and LMLO being tied to VPS2.
The limiter output current is set by the equation:
and has an absolute accuracy of 5%.
The voltage on each of the limiter pins will be given by:
The limiter current may be set as high as 10 mA, which requires
R
beyond this level. It is inadvisable, however, to use high bias
currents, since the gain of this wide bandwidth signal path is
proportional to it, and the risk of instability is elevated as R
reduced (recommended value is 400 ).
The limiter output is specified for input levels between –78 dBV
and +9 dBV. The output of the limiter will be unstable for levels
below –78 dBV (–65 dBm).
REV. B
LIM
to be 40 ohms, and can be optionally increased somewhat
OUT
LIM
Intercept R1
–102
–103
–90
–90
, from high impedance (open-collector) sources.
, the resistor connected between Pin 9 (LMDR) and
V
LIM
= V
k
3.92 8.87 O/C 1
1.05 9.53 O/C 1
3.92 8.87 20.5 1.05 0.08
1.05 9.53 15.4 1.07 0.1
I
OUT
S
– 400 mV
INPUT
R2
k
= –400 mV/R
LOAD
AD8309 SUPPLY DROPPED TO 3V
Figure 37. Buffered RSSI Output with Slope and Intercept Adjustments
Table II.
0.1 F
10
. The limiter output current is
R4
k
R5
k
R
1
2
3
4
5
6
7
8
LOAD
LIM
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
/R
–88 dBV +12 dBV
0.56
0.75
AD8309
LIM
V
OUT
LMDR
VLOG
LMLO
PADL
PADL
VPS2
FLTR
LMHI
(V) at
15
13
12
10
4.56
5.75
4.08
5.10
16
14
11
9
0.1 F
10
LIM
R
is
D
–17–
= (V
SLOPE
S
VR1
2k
High Output Limiter Loading
The AD8309 can generate a fairly large output power at its
differential limiter output interface. This may be coupled into a
50
following similar lines to those provided for input matching.
Alternatively, a flux-linked transformer, having a center-tapped
primary, may be used. Even higher output powers can be ob-
tained using emitter-followers. In Figure 38, the supply voltage
to the AD8309 is dropped from 5 V to about 4.2 V, by the
diode. This increases the available swing at each output to about
2 V. Taking both outputs differentially, a square wave output of
4 V p-p can be generated.
When operating at high output power levels and high frequen-
cies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is
low, due to the extremely high gain-bandwidth product of the
AD8309 under such conditions. These oscillations will be less
evident when signal-balancing networks are used, operating at
frequencies below 200 MHz, and they will generally be fully
quenched by the signal at input levels of a few dB above the
noise floor.
–3V)/25mA
R1
R2
0.1 F
10
10k
grounded load using the narrow-band coupling network
VR2
INT
Figure 38. Increasing Limiter Output Voltage
33.2k
1
2
3
4
5
6
7
8
R3
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
R5
R4
APPROX. 4.2V
AD8309
AD8031
LMDR
VLOG
LMLO
PADL
PADL
VPS2
FLTR
LMHI
0.1 F
1.96k
R6
16
15
14
13
12
11
10
9
10
R
GND
LIM
0.1 F
RSSI
V
S
IN914
R
RSSI
LOAD
R
SET R
LOAD
AD8309
+5V
3V TO 5V
5V TO 3V
DIFFERENTIAL
OUTPUT = 4V pk-pk
L
= 5*R
LIM