AD8306 Analog Devices, AD8306 Datasheet
AD8306
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AD8306 Summary of contents
Page 1
... A CMOS-compatible control interface can enable the AD8306 within about 500 ns and disable standby current of under 1 A. The six cascaded amplifier/limiter cells in the main path have a small signal gain of 12. 4), with a – ...
Page 2
... Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17. ...
Page 3
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8306 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 4
... AD8306 –Typical Performance Characteristics 100 + 0 + 0.01 0.001 0.0001 0.00001 0.5 0.7 0.9 1.1 1.3 1.5 ENABLE VOLTAGE – V Figure 1. Supply Current vs. Enable Voltage @ T = –40 C, +25 C and + ADDITIONAL SUPPLY CURRENT LIMITER OUTPUT 2 CURRENT 100 150 200 250 R – LIM Figure 2 ...
Page 5
... C, for Figure 12. Log Linearity of RSSI Output vs. Input Level +25 C, for Frequencies of 200 MHz, 300 MHz and A 400 MHz –5– AD8306 – –100 –80 –60 –40 –20 0 (– ...
Page 6
... AD8306 100 200 FREQUENCY – MHz Figure 13. RSSI Slope vs. Frequency Using Termination of 52.3 0.4 0.375 0.35 0.325 0.3 0.275 0. 100 150 200 250 FREQUENCY – MHz Figure 14. RSSI Slope Standard Deviation vs. Frequency LMLO LMHI LIMITER OUTPUTS: 50mV PER VERTICAL DIVISION INPUT: 1mV PER VERTICAL DIVISION 12 ...
Page 7
... It follows well-developed foundations proven over a period of some fifteen years, with constant refine- ment. The backbone of the AD8306 (Figure 19) comprises a chain of six main amplifier/limiter stages, each having a gain of 12. and small-signal –3 dB bandwidth of 850 MHz. ...
Page 8
... E mended, even when only one output pin is used, and these should always be returned to the same well decoupled node on the PC board. When the AD8306 is used only to generate an RSSI output, the limiter should be completely disabled by omitting R TO STAGES 1 THRU 5 ...
Page 9
... V level will be as long for load. This may be reduced by adding a grounded load resistance. USING THE AD8306 The AD8306 exhibits very high gain from 1 MHz to over 1 GHz, at which frequency the gain of the main path is still over 65 dB. Consequently susceptible to all signals, within this very broad frequency range, that find their way to the input termi- nals ...
Page 10
... Slope and Intercept. The logarithmic slope is defined as the change in the RSSI output voltage for change at the input. For the AD8306 the slope is calibrated mV/dB. The intercept is the point at which the extrapolated linear re- sponse would intersect the horizontal axis. For the AD8306 the intercept is calibrated to be – ...
Page 11
... The very high frequency attenuation is relatively small, however, since in the limiting = 50 , the limiter output case it is determined simply by the ratio of the AD8306’s input capacitance to the coupling capacitors. Table I provides solu- tions for a variety of center frequencies f ...
Page 12
... Simple schemes can be used to increase and decrease the loga- = 100 MHz rithmic slope as shown in Figure 30. For the AD8306, only IN power, ground and logarithmic output connections are shown; refer to Figure 24 for complete circuitry. In Figure 30(a), the op amp’s gain of +2 increases the slope to 40 mV/dB. In Figure ...
Page 13
... Even higher output powers can be ob- tained using emitter-followers. In Figure 31, the supply voltage to the AD8306 is dropped from about 4 the diode. This increases the available swing at each output to about 2 V. Taking both outputs differentially, a square wave output p-p can be generated ...
Page 14
... Component Function SW1 Device Enable. When in Position A, the ENBL pin is connected to +V AD8306 is in normal operating mode. In Position B, the ENBL pin is connected to an SMA connector labeled Ext Enable. A signal can be applied to this connector to enable/disable the AD8306. R1 This pad is used to ac-couple INLO to ground for single-ended input drive. To drive the AD8306 differentially, R1 should be removed ...
Page 15
... Figure 34. Layout of Signal Layer Figure 35. Layout of Power Layer REV. A Figure 36. Signal Layer Silkscreen Figure 37. Power Layer Silkscreen –15– AD8306 ...
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... AD8306 0.1574 (4.00) 0.1497 (3.80) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Narrow Body SO (SO-16) 0.3937 (10.00) 0.3859 (9.80 0.2440 (6.20) 0.2284 (5.80 PIN 1 0.0688 (1.75) 0.050 (1.27) BSC 0.0532 (1.35) 0.0098 (0.25) 0.0192 (0.49) SEATING 0.0099 (0.25) PLANE 0.0040 (0.10) 0.0138 (0.35) 0.0075 (0.19) –16– 0.0196 (0.50) 45 0.0099 (0.25 0.0500 (1.27) 0.0160 (0.41) REV. A ...