AD811A Analog Devices, AD811A Datasheet - Page 13

• Manufacturer Part Number: AD811A
• Description: High Performance Video op Amp
• Manufacturer: Analog Devices

A Video Keyer Circuit
By using two AD834 multipliers, an AD811, and a 1 V dc
source, a special form of a two-input VCA circuit called a
video keyer can be assembled. “Keying” is the term used in
reference to blending two or more video sources under the
control of a third signal or signals to create such special effects
as dissolves and overlays. The circuit shown in Figure 41 is a
two-input keyer, with video inputs V
input V
given by:
where G is a dimensionless variable (actually, just the gain of
the “A” signal path) that ranges from 0 when V
when V
and V
Circuit operation is straightforward. Consider first the signal
path through U1, which handles video input V
clearly zero when V
ensures that it is unity when V
first term of the transfer function. On the other hand, the V
input to U2 is taken to the inverting input X2 while X1 is
biased at an accurate +1 V. Thus, when V
to video input V
whereas when V
This generates the second term.
REV. D
B
G
G
as G varies from 0 to 1.
. The transfer function (with V
V
(0 TO +1V dc)
= +1 V. Thus, V
G
( 1V FS)
V
A
113
B
G
R5
is already at its full-scale value of unity,
= +1 V, the differential input X1–X2 is zero.
V
G
( 1V FS)
OUT
V
= 0 and the scaling we have chosen
B
1.02k
1.87k
100
174
= G V
R1
R2
R3
R4
OUT
+5V
G
AD589
A
varies continuously between V
U4
= +1 V; this takes care of the
+ (1–G) V
A
226
R6
and V
OUT
G
X2
X2
Y1
Y1
B
8
1
8
1
Figure 41. A Practical Video Keyer Circuit
at the load) is
= 0, the response
B
, and a control
Y2
Y2
A
AD834
AD834
7
X1 +V
2
7
X1 +V
2
G
. Its gain is
U1
U1
= 0, to 1
–V
–V
–5V
+5V
–5V
6
3
6
3
S
S
S
S
R7
45.3
W1
W2
W1
W2
4
4
5
5
G
A
–13–
The bias currents required at the output of the multipliers are
provided by R8 and R9. A dc-level-shifting network comprising
R10/R12 and R11/R13 ensures that the input nodes of the
AD811 are positioned at a voltage within its common-mode
range. At high frequencies C1 and C2 bypass R10 and R11
respectively. R14 is included to lower the HF loop gain, and is
needed because the voltage-to-current conversion in the
AD834s, via the Y2 inputs, results in an effective value of the
feedback resistance of 250 ; this is only about half the value
required for optimum flatness in the AD811’s response. (Note
that this resistance is unaffected by G: when G = 1, all the
feedback is via U1, while when G = 0 it is all via U2). R14
reduces the fractional amount of output current from the multi-
pliers into the current-summing inverting input of the AD811,
by sharing it with R8. This resistor can be used to adjust the
bandwidth and damping factor to best suit the application.
To generate the 1 V dc needed for the “1–G” term an AD589
reference supplies 1.225 V
ing of resistors R2 through R4. Potentiometer R3 should be
adjusted to provide exactly +1 V at the X1 input.
In this case, we have shown an arrangement using dual supplies
of 5 V for both the AD834 and the AD811. Also, the overall
gain in this case is arranged to be unity at the load, when it is
driven from a reverse-terminated 75
“dual VCA” has to operate at a maximum gain of 2, rather
0.1 F
C1
R8
29.4
R9
29.4
2.49k
2.49k
0.1 F
R11
R10
C2
+5V
SEE TEXT
R14
R12
6.98k
R13
6.98k
–5V
TO PIN 6
SETUP FOR DRIVING
REVERSE-TERMINATED LOAD
AD811
TO Y2
AD811
FB
FB
U3
25 mV to a voltage divider consist-
–5V
+5V
0.1 F
0.1 F
C3
200
C4
200
Z
O
line. This means that the
LOAD
GND
LOAD
GND
INSET
V
OUT
Z
O
AD811
V
OUT