XC9500XV Xilinx Corp., XC9500XV Datasheet - Page 4

• Manufacturer Part Number: XC9500XV
• Description: XC9500XV 2.5 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XV Family High-Performance CPLD
Macrocell
Each XC9500XV macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
4
54
Figure 3: XC9500XV Macrocell Within Function Block
Allocator
Note: See
Product
Term
Figure
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
3.
Product Term Clock Enable
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
Figure 8
1
0
www.xilinx.com
1-800-255-7778
for additional clock enable details
Set/Reset
Global
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Clocks
Global
3
EC
D/T
R
S
Preliminary Product Specification
Q
DS049 (v2.1) June 24, 2002
OUT
PTOE
To
Fast CONNECT II
Switch Matrix
DS049_03_041400
To
I/O Blocks
R