XC9500 Xilinx Corp., XC9500 Datasheet - Page 3

• Manufacturer Part Number: XC9500
• Description: XC9500 5 V CPLD Family
• Manufacturer: Xilinx Corp.

Function Block
Each Function Block, as shown in
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the Fast CONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Thirty-six inputs provide 72 true and com-
plement signals into the programmable AND-array to form
DS063 (v5.1) September 22, 2003
Product Specification
Fast CONNECT II
Switch Matrix
R
From
36
Figure
Programmable
AND-Array
2, is comprised of
Figure 2: XC9500 Function Block
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Allocators
Product
Term
Set/Reset
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
Each FB (except for the XC9536) supports local feedback
paths that allow any number of FB outputs to drive into its
own programmable AND-array without going outside the
FB. These paths are used for creating very fast counters
and state machines where all state registers are within the
same FB.
Global
Macrocell 18
1
Macrocell 1
XC9500 In-System Programmable CPLD Family
Clocks
Global
3
18
18
18
OUT
To Fast CONNECT II
Switch Matrix
PTOE
To I/O Blocks
DS063_02_110501
3