STK14C88-3 Simtek, STK14C88-3 Datasheet - Page 10

• Manufacturer Part Number: STK14C88-3
• Description: 32Kx8 AutoStore nvSRAM
• Manufacturer: Simtek

STK14C88-3
Document Control #ML0015 Rev 0.6
The STK14C88-3 has two separate modes of opera-
tion:
mode, the memory operates as a standard fast
static
from
operation) or from nonvolatile elements to
(the
tions are disabled.
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1μF connected between V
V
sible. As with all high-speed
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88-3 performs a
E and G are low and W and HSB are high. The
address specified on pins A
the 32,768 data byte will be accessed. When the
READ
puts will be valid after a delay of t
#1). If the
be valid at t
cycle #2).The data outputs will repeatedly respond to
address changes within the t
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A
low and HSB is high. The address inputs must be
stable prior to entering the
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled
before the end of an E controlled
It is recommended that G be kept high during the
entire
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
SS
WRITE
, using leads and traces that are as short as pos-
0-7
RECALL
February 2007
SRAM
will be written into the memory if it is valid t
SRAM
RAM
is initiated by an address transition, the out-
WRITE
cycle is performed whenever E and W are
READ
. In nonvolatile mode, data is transferred
ELQV
mode and nonvolatile mode. In
to nonvolatile elements (the
cycle to avoid data bus contention on
operation). In this mode
is initiated by E or G, the outputs will
or at t
GLQV
, whichever is later (
CMOS
0-14
AVQV
WRITE
READ
WLQZ
determines which of
access time without
WRITE
after W goes low.
ICs, normal care-
AVQV
nvSRAM OPERATION
cycle and must
cycle whenever
WRITE
(
.
SRAM
READ
CAP
or t
STORE
SRAM
SRAM
READ
cycle
func-
DVWH
and
DVEH
10
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK14C88-3 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
SOFTWARE NONVOLATILE STORE
The STK14C88-3 software
by executing sequential
from six specific address locations. During the
STORE
data is first performed, followed by a program of the
nonvolatile elements. The program operation copies
the
STORE
disabled until the cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ
The software sequence must be clocked with E con-
trolled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
CC
CAP
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
or between E and system V
SRAM
< V
sequence must be performed:
and
READ
cycle is initiated, further input and output are
cycle an erase of the previous nonvolatile
WRITE
RESET
RECALL
WRITE
data into nonvolatile memory. Once a
SWITCH
s.
STORE
), an internal
STORE
CAP
cycles be used in the sequence,
, a
operation.
, the
SRAM
READ
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
once again exceeds the sense
RECALL
cycle will commence and the
SRAM
STORE
or
STORE
RESTORE
will again be activated for
E
or
RECALL
WRITE
STORE
RECALL
controlled
WRITE
cycle will automatically
READ
data will be corrupted.
initiation, it is impor-
CC
to complete.
cycle, the following
STORE
.
state at the end of
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
will take place.
s from specific
cycle is initiated
accesses inter-
request will be
cycle time has
READ
READ
cycles
cycles