EPC1 Altera Corporation, EPC1 Datasheet - Page 22

• Manufacturer Part Number: EPC1
• Description: Configuration EPROMs For Flex Devices
• Manufacturer: Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet
Notes: to
(1)
(2)
(3)
22
DATA
DCLK
OE
nCS
nCASC
VCC
GND
Pin Name
Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration
This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.
This package is available for EPC1441, EPC1064, and EPC1064V devices only.
The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices
support data cascading for FLEX 8000 devices.
(3)
Table 7
1
2
3
4
6
7, 8
5
PDIP
f
8-Pin
(1)
Pin Number
2
4
8
9
12
20
10
20-Pin
PLCC
Table 7
FLEX 8000 device configuration.
For more information on FLEX 8000 device configuration, see the
following documents:
TQFP
10
15
27
12
Application Note 33 (Configuring FLEX 8000 Devices)
Application Note 38 (Configuring Multiple FLEX 8000 Devices)
32-Pin
31
2
7
describes the pin functions of all configuration devices during
(2)
Drain
I/O
Output
Power
Ground Ground pin. A 0.2- F decoupling capacitor must be
Output Serial data output. The DATA pin is tri-stated before
Input
Open-
Input
Type
Pin
configuration when the nCS pin is high and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK is a clock input when using EPC1, EPC1213,
EPC1064, and EPC1064V configuration devices. Rising
edges on DCLK increment the internal address counter
and present the next bit of data to the DATA pin. The
counter is incremented only if the OE input is held high,
the nCS input is held low, and all configuration data has
not been transferred to the target device.
Output enable (active high) and reset (active low). A low
logic level resets the address counter. A high logic level
enables DATA and permits the address counter to count.
Chip-select input (active low). A low input allows DCLK to
increment the address counter and enables DATA.
Cascade-select output (active low). This output goes low
when the address counter has reached its maximum
value. The nCASC output is usually connected to the nCS
input of the next device in a configuration chain, so the
next DCLK clocks data out of the next device.
Power pin.
placed between the VCC and GND pins.
Description
Altera Corporation