AN296 Silicon_Laboratories, AN296 Datasheet - Page 19

• Manufacturer Part Number: AN296
• Description: Using THE Si3400 AND Si3401 POE PD Controllers IN Isolated AND Non-isolated Designs
• Manufacturer: Silicon_Laboratories

7. Layout, EMI, and EMC Considerations
Refer to the files located at www.silabs.com/PoE under the documentation page for examples of recommended
PCB layouts in the evaluation board user’s guides. Silicon Labs strongly recommends adhering to the layouts
shown in these designs to avoid potential performance issues. In general, four-layer PCB designs yield the most
robust design, as shown in the evaluation board user’s guides. Two-layer PCB designs must be carefully
considered. Silicon Labs strongly recommends all two-layer PCB designs be reviewed before fabrication.
Submit PCB schematics and layout files to [e-mail] for feedback and recommendations on these
designs.
7.1. Thermal Considerations
The thermal pad of the Si3400/01 must be connected to a heat spreader. Generally, a 2 in
connected to the thermal pad of the Si3400/01 and electrically connected to Vneg is recommended. While the heat
spreader generally is not a circuit ground, it is a good reference plane for the Si3400/01 and is also useful as a
shield layer for EMI reduction.
With the 2 in
As an added data point, 54 °C/W was measured with a 1 in
Due to heating of the ambient air from the Schottky diode etc., the effective thermal impedance can be
considerably higher than this. It is not unusual for the Si3400/01 junction temperature to rise 70 °C. The Si3400/01
is rated up to a junction temperature of 140 °C, with thermal shutdown to 160 °C typical. If such a high junction
temperature is a concern, it can be reduced by bypassing the on-chip diode bridges as discussed in “AN313: Using
the Si3400 and Si3401 in High Power Applications". Diode bridge bypass for full-power applications should also be
considered in a two-layer design where it is difficult to include such a large thermal plane.
7.2. Voltage Considerations
Since the Si3400/01 is not exposed to dc voltages over 60 V dc, it is generally considered to be a safety-extra-low-
voltage (SELV) circuit, and there are no particular spacing requirements other than those of high-yield board
manufacture.
7.3. Current Considerations
Pins CT1, CT2, SP1, SP2, HSO, and V
Pins SWO and V
and 25 mil traces are used for these pins. Output current can be up to 3 A depending on output voltage, and 50 mil
traces are recommended in the output section.
7.4. EMI and EMC Considerations
As with any switching converter, care in the overall circuit design and layout is required to meet the stringent
requirements for EMI (i.e CISPR 22 Class B in the 30 MHz to 1 GHz band) and EMC (i.e. EN55022 in the 150 kHz
to 30 MHz band). While the comments in this section apply to both the isolated flyback approach and non-isolated
topologies, the flyback topology is the most challenging and, therefore, the focus of the discussion.
To prevent radiated emissions, care must be taken to keep the circuit nodes with high ac voltage very short and to
keep the current loops carrying high ac current of a very small diameter.
Referring to Figure 4, the circuit nodes with high voltage swing are as follows:
These circuit nodes should be kept extremely short to minimize EMI. While the current flowing is fairly high (about
1 A on the primary side and 3 A on the secondary side), trace width should be limited to about 25 mils to cut down
on radiation. While it is possible to reduce radiation by routing these nodes on an inner layer, in practice, it should
be possible to arrange the layout so that these two nodes are sufficiently short that there is little advantage to be
gained by this. An R-C snubber across the transformer primary or across the output rectifier can reduce dV/dt and
thus radiation. In practice, it has been found that the secondary side snubber is quite effective, but the primary side
snubber is not helpful in this regard due to the high current peak associated with switcher FET turn on in the case
of the primary side snubber.
The node connecting SWO (Si3400/01 pin 18) and the transformer primary
The node connecting the transformer secondary to the anode of D2
2
thermal plane on an outer layer, the thermal impedance of the Si3400/01 was measured at 44 °C/W.
SS
carry current spikes of up to several amps, although the dc current is no more than 325 mA,
POSF
carry up to 325 mA dc. 12 mil traces have been found to be adequate.
Rev. 0.8
2
plane on an inner layer.
2
AN296
bottom plane
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