ADSP-BF531 Analog Devices, ADSP-BF531 Datasheet - Page 5

• Manufacturer Part Number: ADSP-BF531
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices

0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
Figure 3. ADSP-BF533 Internal/External Memory Map
LD0 32 BITS
LD1 32 BITS
SD 32 BI TS
SDRAM MEMORY (16M BYTE TO 128M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
RESERVED
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM (16K BYTE)
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
RESERVED
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (64K BYTE)
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK A SRAM / CACHE (16K BYTE)
R7
R6
R5
R4
R3
R2
R1
R0
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
SP
FP
P5
P4
P3
P2
P1
P0
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
I 3
I 2
I 1
I 0
BARREL
SHIFTER
8
L3
L2
L1
L0
Rev. 0 | Page 5 of 56 | March 2004
ADDRE SS ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
DATA ARITHME TIC UNI T
A 0
16
B3
B2
B1
B0
40
M3
M2
M1
M0
8
ADSP-BF531/ADSP-BF532/ADSP-BF533
8
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
DAG0
Figure 4. ADSP-BF532 Internal/External Memory Map
A1
16
40
DAG 1
8
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (32K BYTE)
RESERVED
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
RESERVED
SDRAM MEMORY (16M BYTE TO 128M BYTE)
LOO P BUF FE R
S EQUENCER
CONTRO L
DECO DE
ALIG N
UNIT