AD1839A Analog Devices, AD1839A Datasheet - Page 22

• Manufacturer Part Number: AD1839A
• Description: 2 ADC, 6 DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

AD1839A
CASCADE MODE
Dual AD1839A Cascade
The AD1839A can be cascaded to an additional AD1839A
which, in addition to six external stereo ADCs and two external
stereo DACs, can be used to create a 32-channel audio system
with 16 inputs and 16 outputs. The cascade is designed to
connect to a SHARC DSP and operates in a time division
multiplexing (TDM) format. Figure 14 shows the connection
diagram for cascade operation. The digital interface for both
parts must be set to operate in Auxiliary 512 mode by program-
ming ADC Control Register 2. AD1839A No. 1 is set as a
master device by connecting the M/S pin to DGND; AD1839A
No. 2 is set as a slave device by connecting the M/S to ODVDD.
Both devices should be run from the same MCLK and PD/RST
signals to ensure that they are synchronized.
(SLAVE)
SHARC
DRx
TFSx/
DTx
RFSx
BCLK
RCLKx
TCLKx
DTx
DRx
RFSx
TFSx
DRx
DTx
L1
L1
AUX ADC
(SLAVE)
L2
L2
MSB
MSB
ASDATA
ALRCLK
ABCLK
AD1839A NO. 1 DACs
AD1839A NO. 1 ADCs
Figure 15. Dual AD1839A Cascade Timing
L3
L3
MSB – 1
MSB – 1
256 ABCLKs
Figure 14. Dual AD1839A Cascade
L4
AUX ADC
L4
(SLAVE)
R1
R1
32 ABCLKs
R2
R2
AD1839A NO. 1
LSB
LSB
(MASTER)
AUX ADC
(SLAVE)
R3
R3
DSDATA
–22–
R4
R4
DON’T CARE
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2, ensuring that both know when to send and receive data.
The cascade can be thought of as two 256 bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending DAC
data to the second shift register. By the end of the sample interval,
all 512 bits of ADC data in the shift registers will have been
clocked into the SHARC and replaced by DAC data, which is
subsequently written to the DACs. Figure 15 shows the timing
diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
AD1839A NO. 2 DACs
AD1839A NO. 2 ADCs
L3
L3
256 ABCLKs
ASDATA
ALRCLK
ABCLK
L4
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1839A NO. 2
(SLAVE)
AUX ADC
R4
R4
(SLAVE)
DSDATA
REV. A