AD1839 Analog Devices, AD1839 Datasheet - Page 20

• Manufacturer Part Number: AD1839
• Description: 2 ADC, 6 DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

AD1839
CASCADE MODE
Dual AD1839 Cascade
The AD1839 can be cascaded to an additional AD1839 which,
in addition to six external stereo ADCs can be used to create a
28-channel audio system with 16 inputs and 12 outputs. The
cascade is designed to connect to a SHARC DSP and operates
in a Time Division Multiplexing (TDM) format. Figure 14
shows the connection diagram for cascade operation. The digital
interface for both parts must be set to operate in Auxiliary
512 mode by programming ADC Control Register II. AD1839
#1 is set as a master device by connecting the
and AD1839 #2 is set as a slave device by connecting the
DVDD. Both devices should be run from the same MCLK and
signals to ensure that they are synchronized.
(SLAVE)
SHARC
DRx
DTx
RFSx
BCLK
DTx
DRx
RCLKx
TCLKx
RFSx
PRELIMINARY TECHNICAL DATA
DRx
DTx
L1
L1
AUX ADC
L2
MSB
(SLAVE)
L2
MSB
L3
L3
AD1839 #1 DACs
AD1839 #1 ADCs
MSB-1
ASDATA
ALRCLK
ABCLK
256 BCLKs
MSB-1
/S pin to DGND
L4
AUX ADC
(SLAVE)
Figure 15. Cascade Timing
R1
R1
32 ABCLKs
Figure 14. Cascade
R2
R2
LSB
LSB
/S to
R3
AD1839 #1
R3
(MASTER)
AUX ADC
(SLAVE)
DSDATA
–20–
R4
DON’ T CARE
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2 ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers,
one for each device. At the beginning of a sample interval the
shift registers contain the ADC results from the previous
sample interval. The first shift register (Device 1) clocks data
into the SHARC and also clocks in data from the second shift
register (Device 2). While this is happening, the SHARC is
sending DAC data to the second shift register. By the end of
the sample interval all 512 bits of ADC data in the shift regis-
ters will have been clocked into the SHARC and been replaced
by DAC data which is subsequently written to the DACs.
Figure 15 shows the timing diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
L3
L3
AD1839 #2 DACs
AD1839 #2 ADCs
256 BCLKs
ASDATA
ALRCLK
ABCLK
L4
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1839 #2
(SLAVE)
AUX ADC
(SLAVE)
DSDATA
R4
REV. PrD