AD1833A Analog Devices, AD1833A Datasheet - Page 16

• Manufacturer Part Number: AD1833A
• Description: Multi-Channel, 24-Bit, 192 KHZ Sigma-delta DAC
• Manufacturer: Analog Devices

L/RCLK
AD1833A
Packed Mode 128
In Packed Mode 128, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 128
therefore, there are 128 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots: six slots of
20 BCLK and two of 4 BCLK. In this mode, the data length is
restricted to a maximum of 20 bits. The three left channels are
written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLK, and then the three right channels are writ-
ten. The L/RCLK defines the left and right data transmission; it
is high for the three left channels and low for the three right channels.
L/RCLK
BCLK
DATA
BCLK
DATA
24-BIT DATA
20-BIT DATA
16-BIT DATA
BCLK
SLOT 1
LEFT 0
SLOT 1
LEFT 0
MSB
MSB
MSB
MSB
MSB
MSB
–1
–1
–1
MSB
SLOT 2
MSB
MSB
LEFT 1
–2
–2
–2
SLOT 2
LEFT 1
MSB
MSB
MSB
–3
–3
–3
20-BIT DATA
16-BIT DATA
MSB
MSB
MSB
–4
–4
–4
SLOT 3
LEFT 2
BCLK
SLOT 3
LEFT 2
Figure 11. Packed Mode 128
Figure 12. Packed Mode 256
MSB
MSB
LSB
LSB
LSB
+8
+4
BLANK SLOT
MSB
MSB
LSB
LSB
4 SCLK
–1
–1
+7
+3
f
S
;
MSB
MSB
LSB
LSB
–2
–2
+6
+2
–16–
MSB
MSB
LSB
LSB
–3
–3
+5
+1
Packed Mode 256
In Packed Mode 256, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 256
therefore, there are 256 BCLK periods in each sample interval, and
each sample interval is broken into eight time slots of 32 BCLK
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on the
falling edge of BCLK with a one BCLK period delay from the
start of the slot. After the three left channels are written, there is
a space of 32 BCLK, and then the three right channels are written.
The L/RCLK defines the left and right data transmission; it is
low for the three left channels and high for the three right channels.
RIGHT 0
SLOT 4
RIGHT 0
SLOT 4
MSB
MSB
LSB
LSB
–4
–4
+4
LSB
+3
LSB
+2
RIGHT 1
SLOT 5
RIGHT 1
LSB
LSB
SLOT 5
+4
LSB
+1
LSB
+3
LSB
LSB
+2
RIGHT 2
SLOT 6
RIGHT 2
SLOT 6
LSB
+1
LSB
BLANK SLOT
4 SCLK
REV. 0
f
S
;