ADS8322YB Burr-Brown Corporation, ADS8322YB Datasheet - Page 7

• Manufacturer Part Number: ADS8322YB
• Description: 16-Bit/ 500kHz/ MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

THEORY OF OPERATION
The ADS8322 is a high-speed Successive Approximation
Register (SAR) A/D converter with an internal 2.5V bandgap
reference. The architecture is based on capacitive redistribu-
tion which inherently includes a sample-and-hold function.
The basic operating circuit for the ADS8322 is shown in
Figure 1.
The ADS8322 requires an external clock to run the conver-
sion process. The clock can be run continuously or it can be
gated to conserve power between conversions. This clock
can vary between 25kHz (1.25kHz throughput) and 10MHz
(500kHz throughput). The duty cycle of the clock is unim-
portant as long as the minimum HIGH and LOW times are
at least 40ns and the clock period is at least 100ns. The
minimum clock frequency is governed by the parasitic
leakage of the Capacitive Digital-to-Analog (CDAC) ca-
pacitors internal to the ADS8322.
The analog input is provided to two input pins, +IN and –IN.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
FIGURE 1. Typical Circuit Configuration.
ADS8322
SBAS215
1
2
3
4
5
6
7
8
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
32
9
31
10
0.1 F
30
11
+5V Analog Supply
ADS8322
29
12
28
13
0.1 F
10 F
+
27
14
26
15
REFERENCE
Under normal operation, the REF
connected to the REF
reference to the ADS8322. The ADS8322 can operate,
however, with an external reference in the range of 1.5V to
2.6V for a corresponding full-scale range of 3.0V to 5.2V.
The internal reference of the ADS8322 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load ap-
plied to the REF
source and sink 10 A of current). If an external reference is
used, the second buffer provides isolation between the exter-
nal reference and the CDAC. This buffer is also used to
recharge all of the CDAC capacitors during conversion.
ANALOG INPUT
When the converter enters Hold mode, the voltage differ-
ence between the +IN and –IN inputs is captured on the
internal capacitor array. The voltage on the –IN input is
25
16
CONVST
CLOCK
DGND
BUSY
BYTE
+V
RD
CS
D
24
23
22
21
20
19
18
17
OUT
pin (the internal reference can typically
IN
pin to provide an internal +2.5V
+
–
Chip Select
Read Input
Conversion Start
Clock Input
Busy Output
Analog Input
OUT
pin should be directly
7