ADS7816C Burr-Brown Corporation, ADS7816C Datasheet - Page 10

• Manufacturer Part Number: ADS7816C
• Description: 12-Bit High Speed Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
DATA FORMAT
The output data from the ADS7816 is in Straight Binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
Table II. Ideal Input Voltages and Output Codes.
DESCRIPTION
Full Scale Range
Least Significant
Bit (LSB)
Full Scale
Midscale
Midscale – 1 LSB
Zero
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Waveform 1
Waveform 2
CS/SHDN
DCLOCK
D
D
D
OUT
OUT
OUT
(1)
(2)
®
Voltage Waveforms for D
ADS7816
ANALOG VALUE
Voltage Waveforms for t
V
t
hDO
V
REF
D
V
Load Circuit for t
REF
OUT
REF
V
/2 – 1 LSB
V
REF
0V
–1 LSB
REF
/4096
/2
V
IL
t
dDO
1.4V
dDO
3k
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
100pF
C
BINARY CODE
OUT
LOAD
, t
t
dis
dis
r
Delay Times, t
, and t
STRAIGHT BINARY
DIGITAL OUTPUT:
Test Point
f
V
IH
90%
10%
dDO
HEX CODE
FFF
7FF
800
000
V
V
OH
OL
10
D
OUT
CS/SHDN
Voltage Waveforms for D
DCLOCK
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7816 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7816 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
In addition, the ADS7816 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
t
D
r
OUT
D
OUT
Test Point
100pF
C
LOAD
Load Circuit for t
3k
OUT
Voltage Waveforms for t
Rise and Fall TImes t
1
dis
and t
V
CC
den
2
t
f
t
t
dis
dis
en
r
t
, and t
en
Waveform 2, t
Waveform 1
V
V
V
OL
OH
OL
f
B11
en