ADS7810 Burr-Brown Corporation, ADS7810 Datasheet - Page 4

• Manufacturer Part Number: ADS7810
• Description: 12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

PIN ASSIGNMENTS
PIN CONFIGURATION
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
D11 (MSB)
AGND1
AGND2
DGND
®
D11 (MSB)
CAP
D0 (LSB)
REF
D10
AGND1
AGND2
NAME
DGND
DGND
V
+V
BUSY
+V
D9
D8
D7
D6
D5
D4
+V
–V
+V
REF
CAP
ADS7810
D10
R/C
IN
NOTE: (1) Not Internally Connected.
V
D9
D8
D7
D6
D5
D4
D3
D2
D1
CS
IN
ANA
ANA
ANA
DIG
DIG
10
11
12
13
14
1
2
3
4
5
6
7
8
9
DIGITAL
ADS7810
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
DESCRIPTION
Analog Input. Connect via 50
Analog Ground. Used internally as ground reference point. Minimal current flow.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1 F ceramic capacitor.
Reference Buffer Output. 10 F tantalum capacitor to ground. Nominally +2V.
Analog Ground.
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
Not internally connected.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
Digital ground.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With
R/C HIGH and no conversion in progress, a falling edge on CS will enable the output data bits.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1 F ceramic and 10 F tantulum
capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1 F ceramic and 10 F tantulum capacitors.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+V
+V
–V
BUSY
CS
R/C
DGND
+V
+V
NC
D0 (LSB)
D1
D2
D3
ANA
ANA
DIG
DIG
ANA
(1)
to analog input. Full-scale input range is 10V.
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