16C6NL Renesas Technology / Hitachi Semiconductor, 16C6NL Datasheet - Page 47
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16C6NL
Manufacturer Part Number
16C6NL
Description
Renesas MCU
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.16C6NL.pdf
(70 pages)
- Current page: 47 of 70
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M16C/6N Group (M16C/6NL, M16C/6NN)
Rev.2.10
REJ03B0061-0210
Under development
This document is under development and its contents are subject to change.
Figure 5.6 Timing Diagram (4)
Aug 25, 2006
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Measuring conditions :
tcyc =
WR,WRL,
WRH
Read timing
Write timing
BCLK
BCLK
VCC = 5 V
Input timing voltage : V
Output timing voltage : V
CSi
CSi
BHE
BHE
ADi
ADi
ALE
ALE
DBi
RD
DBi
f(BCLK)
1
page 47 of 67
t
Hi-Z
t
t
d(BCLK-ALE)
d(BCLK-ALE)
d(BCLK-CS)
t
t
d(BCLK-CS)
d(BCLK-AD)
t
25ns.max
25ns.max
d(BCLK-AD)
25ns.max
25ns.max
25ns.max
25ns.max
tcyc
tcyc
IL
OL
t
h(BCLK-ALE)
= 0.8 V, V
Hi-Z
= 0.4 V, V
t
t
h(BCLK-ALE)
d(BCLK-RD)
-4ns.min
25ns.max
-4ns.min
IH
OH
(1.5 ✕ tcyc-45)ns.max
= 2.0 V
t
d(BCLK-WR)
= 2.4 V
(0.5 ✕ tcyc-40)ns.min
t
t
ac2(RD-DB)
d(BCLK-DB)
25ns.max
40ns.max
t
d(DB-WR)
(0.5 ✕ tcyc-10)ns.min
t
SU(DB-RD)
40ns.min
t
t
h(BCLK-WR)
h(WR-AD)
0ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
0ns.min
h(RD-AD)
t
h(BCLK-CS)
t
h(BCLK-CS)
t
t
t
t
h(BCLK-DB)
h(BCLK-AD)
h(BCLK-RD)
h(BCLK-AD)
4ns.min
4ns.min
0ns.min
4ns.min
4ns.min
4ns.min
t
h(RD-DB)
0ns.min
5. Electric Characteristics
VCC = 5 V
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