16C62P Renesas Technology / Hitachi Semiconductor, 16C62P Datasheet - Page 32
16C62P
Manufacturer Part Number
16C62P
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.16C62P.pdf
(101 pages)
- Current page: 32 of 101
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ03B0001-0241
2.8.8
2.8.9
2.8.10
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
When write to this bit, write “0”. When read, its content is indeterminate.
Jan 10, 2006
Stack Pointer Select Flag (U Flag)
Processor Interrupt Priority Level (IPL)
Reserved Area
Page 32 of 96
2. Central Processing Unit (CPU)
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