ATA6834 ATMEL Corporation, ATA6834 Datasheet - Page 8

• Manufacturer Part Number: ATA6834
• Description: (ATA6833 / ATA6834) BLDC Motor Driver and LIN System Basis Chip
• Manufacturer: ATMEL Corporation

3.4
Figure 3-4.
8
88% VCC
Reset and Watchdog Management
ATA6833/ATA6834 [Preliminary]
VCC
WD
/RESET
Timing Diagram of the Watchdog in Conjunction with the /RESET Signal
Reset and lead
time, no trigger
t
The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time T
is determined by the external resistor R
function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor
the watchdog is enabled by default. In order to keep the current consumption as low as possible
the watchdog is switched off during Sleep Mode.
The timing diagram in
After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET
output stays LOW for the timeout period t
switches to HIGH. During the following time t
expected otherwise another external reset will be triggered.
When the watchdog has been correctly triggered for the first time, normal watch-dog operation
begins. A normal watchdog cycle consists of two time sections t
for the time t
edges on WD pin during t
the time of the last rising edge either on WD pin or on /RESET pin.
If the watchdog is disabled (WDD = LOW), only the initial reset for the time t
will be generated.
Additional resets will be generated if the VCC output voltage drops below 80% of its nominal
value.
The following example demonstrates how to calculate the timing scheme for valid watchdog trig-
ger pulses, which the external microcontroller has to provide in order to prevent undesired
resets.
res
t
d
trigger during lead time
resshort
Reset and lead time,
t
res
at /RESET if no valid trigger has been applied at pin WD during t
Figure 3-4
t
d
trigger edge
Watchdog
1
also cause a short pulse on /RESET. Start for such a cycle is always
Watchdog cycle,
shows the watchdog and external reset timing.
t
1
no trigger
WD
. A HIGH signal on WDD pin enables the watchdog
t
res
2
d
(typical 500 ms) a rising edge at the input WD is
(typical 10 ms). Subsequently /RESET output
t
Watchdog cycle, trigger
resshort
t
during t
1
1
and t
2
window
2
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followed by a short pulse
Watchdog trigger
t
2
in t
2
res
window
9122D–AUTO–09/09
after power-up
t
1
2
. Rising
OSC