MAX9853 Maxim Integrated Products, MAX9853 Datasheet - Page 61

• Manufacturer Part Number: MAX9853
• Description: (MAX9851 / MAX9853) Stereo Audio CODECs
• Manufacturer: Maxim Integrated Products

One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 11). A
START condition from the master signals the beginning
of a transmission to the MAX9851/MAX9853. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
The MAX9851/MAX9853 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Figure 11. START, STOP, and REPEATED START Conditions
Stereo Audio CODECs with Microphone, DirectDrive
2
C bus is not busy.
SCL
SDA
Headphones, Speaker Amplifiers, or Line Outputs
S
______________________________________________________________________________________
START and STOP Conditions
Sr
Early STOP Conditions
Bit Transfer
P
The MAX9851/MAX9853 are preprogrammed with a
slave address of 0x20 or 0010000. The address is
defined as the 7 most significant bits (MSBs) followed by
the read/write bit. Set the read/write bit to 1 to configure
the MAX9851/MAX9853 to read mode. Set the read/write
bit to 0 to configure the MAX9851/MAX9853 to write
mode. The address is the first byte of information sent to
the MAX9851/MAX9853 after the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9851/MAX9853 use to handshake receipt each byte
of data when in write mode (see Figure 12). The
MAX9851/MAX9853 pull down SDA during the entire
master-generated ninth clock pulse if the previous byte is
successfully received. Monitoring ACK allows for detec-
tion of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
The master pulls down SDA during the ninth clock cycle
to acknowledge receipt of data when the MAX9851/
MAX9853 are in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9851/
MAX9853, followed by a STOP condition.
Figure 12. Acknowledge
SDA
SCL
CONDITION
START
1
2
NOT ACKNOWLEDGE
ACKNOWLEDGE
ACKNOWLEDGMENT
8
CLOCK PULSE FOR
Slave Address
Acknowledge
9
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