MAX9598 Maxim Integrated Products, MAX9598 Datasheet - Page 18

• Manufacturer Part Number: MAX9598
• Description: Low-Power Audio/Video Switch
• Manufacturer: Maxim Integrated Products

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SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 7). A START
condition from the master signals the beginning of a
transmission to the MAX9598. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
The MAX9598 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
The slave address is defined as the 7 MSBs (most sig-
nificant bits) followed by the R/W (read/write) bit. Set
the R/W bit to 1 to configure the MAX9598 to read
mode. Set the R/W bit to 0 to configure the MAX9598 to
Low-Power Audio/Video Switch for
Dual SCART Connectors
18
Figure 7. START, STOP, and REPEATED START Conditions
Table 3. Slave Address
DEV_ADDR
SCL
SDA
______________________________________________________________________________________
GND
VVID
SDA
SCL
S
B7
1
1
1
1
START and STOP Conditions
B6
0
0
0
0
Sr
Early STOP Conditions
B5
0
0
0
0
B4
1
1
1
1
Slave Address
B3
0
0
1
1
P
B2
1
1
0
0
B1
0
1
0
1
write mode. The slave address is always the first byte
of information sent to the MAX9598 after a START or a
REPEATED START condition. The MAX9598 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the MAX9598.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9598 uses to handshake receipt of each byte of
data when in write mode (see Figure 8). The MAX9598
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a
receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the 9th clock cycle to acknowl-
edge receipt of data when the MAX9598 is in read mode.
An acknowledge is sent by the master after each read
byte to allow data transfer to continue. A not acknowl-
edge is sent when the master reads the final byte of data
from the MAX9598, followed by a STOP condition.
Figure 8. Acknowledge
SDA
SCL
CONDITION
R/W
R/W
R/W
R/W
START
B0
WRITE ADDRESS
1
(hex)
9Ah
94h
96h
98h
2
NOT ACKNOWLEDGE
ACKNOWLEDGE
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
READ ADDRESS
Acknowledge
(hex)
9Bh
95h
97h
99h
9