MAX9215 Maxim Integrated Products, MAX9215 Datasheet - Page 12

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MAX9215

Manufacturer Part Number
MAX9215
Description
(MAX9209 - MAX9215) Programmable DC-Balanced 21-Bit Serializers
Manufacturer
Maxim Integrated Products
Datasheet
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
Programmable DC-Balanced
21-Bit Serializers
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
12
PWRDWN
______________________________________________________________________________________
TxCLK IN
TxIN
CYCLE N - 1
TxIN15
TxCLK OUT+
TxCLK OUT-
TxOUT2
TxOUT1
TxOUT0
TxIN8
TxIN1
7
7
7
TxIN14
TxIN7
TxIN0
TxIN20
TxIN13
PLL
TxIN6
7:1
7:1
7:1
21:3 SERIALIZER
MAX9209
MAX9211
MAX9213
MAX9215
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
CYCLE N
TxIN17
TxIN10
TxIN3
R
R
R
R
O
O
O
O
TxIN16
TxIN9
TxIN2
TxOUT
TxCLK OUT
TxIN15
TxIN8
TxIN1
TRANSMISSION LINE
TxIN14
TxIN7
TxIN0
from 0V to 2.4V, allowing approximately ±1V common-
mode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
100Ω
100Ω
100Ω
100Ω
R
R
R
R
RxCLK IN
T
T
T
T
TxIN20
TxIN13
TxIN6
=
=
=
=
RxIN
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
3:21 DESERIALIZER
CYCLE N + 1
MAX9210
MAX9212
MAX9214
MAX9216
TxIN17
TxIN10
TxIN3
TxIN16
PLL
1:7
1:7
1:7
TxIN9
TxIN2
TxIN15
TxIN8
TxIN1
7
7
7
TxIN14
TxIN7
TxIN0
RxOUT
PWRDWN
RxCLK OUT

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