MAX8731A Maxim Integrated Products, MAX8731A Datasheet - Page 20

• Manufacturer Part Number: MAX8731A
• Description: SMBus Level 2 Battery Charger
• Manufacturer: Maxim Integrated Products

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SMBus Level 2 Battery Charger
with Remote Sense
The MAX8731A receives control inputs from the SMBus
interface. The MAX8731A uses a simplified subset of
the commands documented in System Management
Bus Specification V1.1, which can be downloaded from
www.smbus.org. The MAX8731A uses the SMBus
Read-Word and Write-Word protocols (Figure 3) to
communicate with the smart battery. The MAX8731A
performs only as an SMBus slave device with address
0b0001001_ (0x12) and does not initiate communica-
tion on the bus. In addition, the MAX8731A has two
identification (ID) registers (0xFE): a 16-bit device ID
register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trig-
ger inputs that can accommodate slow edges. Choose
pullup resistors (10kΩ) for SDA and SCL to achieve rise
times according to the SMBus specifications.
Figure
20
______________________________________________________________________________________
3. SMBus Write-Word and Read-Word Protocols
S
S
a) WRITE-WORD FORMAT
b) READ-WORD FORMAT
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
MSB
MSB
ADDRESS
PRESET TO
0b0001001
ADDRESS
0b0001001
Preset to
SLAVE
SLAVE
7 BITS
7 BITS
MASTER TO SLAVE
SLAVE TO MASTER
LSB
LSB
W
W
1b
1b
0
0
ACK
ACK
1b
1b
0
0
ChargerMode() = 0x12
ChargeCurrent() = 0x14
ChargeVoltage() = 0x15
AlarmWarning() = 0x16
InputCurrent() = 0x3F
ChargerSpecInfo() = 0x11
ChargerStatus() = 0x13
SMBus Interface
MSB
MSB
COMMAND
COMMAND
8 BITS
8 BITS
BYTE
BYTE
LSB
LSB
ACK
ACK
1b
1b
0
0
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
D7
S
MSB
LOW DATA
MSB
BYTE
8 BITS
ADDRESS
PRESET TO
0b0001001
SLAVE
7 BITS
LSB
D0
Communication starts when the master signals a
START condition, which is a high-to-low transition on
SDA, while SCL is high. When the master has finished
communicating, the master issues a STOP condition,
which is a low-to-high transition on SDA, while SCL is
high. The bus is then free for another transmission.
Figures 4 and 5 show the timing diagram for signals on
the SMBus interface. The address byte, command
byte, and data bytes are transmitted between the
START and STOP conditions. The SDA state changes
only while SCL is low, except for the START and STOP
conditions. Data is transmitted in 8-bit bytes and is
sampled on the rising edge of SCL. Nine clock cycles
are required to transfer each byte in or out of the
MAX8731A because either the master or the slave
acknowledges the receipt of the correct byte during the
ninth clock cycle. The MAX8731A supports the charger
commands as described in
LSB
ACK
1b
0
1b
R
1
D15
ACK
MSB
HIGH DATA
1b
0
BYTE
8 BITS
D7
MSB
LOW DATA
LSB
BYTE
8 BITS
D8
LSB
ACK P
1b
0
D0
ACK
1b
0
D15
Table
MSB
HIGH DATA
BYTE
8 BITS
LSB
4.
D8
NACK P
1b
1