MAX7042 Maxim Integrated Products, MAX7042 Datasheet - Page 8

• Manufacturer Part Number: MAX7042
• Description: 308MHz/315MHz/418MHz/433.92MHz Low-Power FSK Superheterodyne Receiver
• Manufacturer: Maxim Integrated Products

308MHz/315MHz/418MHz/433.92MHz
Low-Power, FSK Superheterodyne Receiver
8
3, 25, 32
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PIN
1, 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
EP
4
5
6
7
8
9
LNAOUT
LNASRC
MIXOUT
LNASEL
MIXIN+
PDMAX
PDMIN
MIXIN-
NAME
XTAL2
XTAL1
LNAIN
AGND
DGND
FSEL1
FSEL2
DV
DATA
AV
IFIN+
HV
GND
RSSI
IFIN-
N.C.
N.C.
DS+
OP+
DS-
DF
EN
DD
DD
IN
No Connection. Internally pulled down.
No Connection. Not internally connected.
Buffered Received-Signal-Strength-Indicator Output
Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference.
Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.
Analog Power-Supply Voltage. AV
Bypass AV
Low-Noise Amplifier Input. Must be AC-coupled.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
Low-Noise Amplifier Output. Connect to AV
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to AV
330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter.
Analog Ground
Inverting 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor.
Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data-Slicer Input
Noninverting Data-Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Digital Ground
Digital Power-Supply Voltage. Bypass to DGND with 0.01µF and 220pF capacitors placed as close to
the pin as possible.
Enable. Internally pulled down. Drive high for normal operation. Drive low or leave unconnected to put
the device into shutdown mode.
Frequency-Select Pin 1 (see Table 1). Internally pulled down. Connect to EN for logic-high operation.
Frequency-Select Pin 2 (see Table 1). Internally pulled down. Connect to EN for logic-high operation.
High-Voltage Supply Input. For +3V operation, connect HV
connect only HV
to the pin as possible.
Receiver Data Output
LNA Bias Current Select Pin. Internally pulled down. Set LNASEL to logic-low for low LNA current and
set LNASEL to logic-high for high LNA current. Connect to EN for logic-high operation.
Exposed Paddle. Connect to ground.
DD
to GND with 0.1µF and 220pF capacitors placed as close to the pin as possible.
IN
to +5V. Bypass HV
DD
DD
is connected to an on-chip +3.0V regulator in +5V operation.
IN
or AGND with a capacitor.
to AGND with 0.01µF and 220pF capacitors placed as close
DD
FUNCTION
through a parallel LC tank filter. AC-couple to MIXIN+.
IN
to AV
DD
and DV
Pin Description
DD
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. For +5V operation,