ADC7802BN Burr-Brown Corporation, ADC7802BN Datasheet - Page 2

• Manufacturer Part Number: ADC7802BN
• Description: Autocalibrating, 4-channel, 12-bit Analog-to-digital Converter
• Manufacturer: Burr-Brown Corporation

SPECIFICATIONS
ELECTRICAL
At V
cycle at any temperature, unless otherwise specified.
NOTES: (1) For (V
sample/hold in front of the ADC7802. (3) After calibration cycle, without external adjustment. Includes gain (full scale) error, offset error, integral nonlinearity,
differential nonlinearity, and drift.
All Pins Other Than CLK: V
PARAMETER
RESOLUTION
ANALOG INPUT
Voltage Input Range
Input Capacitance
On State Bias Current
Off State Bias Current
On Resistance Multiplexer
Off Resistance Multiplexer
Channel Separation
REFERENCE INPUT
For Specified Performance: V
For Derated Performance:
Input Reference Current
THROUGHPUT TIMING
Conversion Time With External Clock (Including
With Internal Clock Using
Analog Signal Bandwidth
Slew Rate
Multiplexer Settling Time to 0.01%
Multiplexer Access Time
ACCURACY
Total Adjusted Error,
Differential Nonlinearity
No Missing Codes
Gain Error
Gain Error Drift
Offset Error
Offset Error Drift
Channel-to-Channel Mismatch
Power Supply Sensitivity
DIGITAL INPUTS
Input Current
CLK Input: V
DIGITAL OUTPUTS
V
V
Leakage Current
Output Capacitance
POWER SUPPLIES
Supply Voltage for Specified Performance: V
Supply Current: I
Power Dissipation
Power Down Mode
TEMPERATURE RANGE
Specification
Storage
OL
OH
Recommended Clock Components
Multiplexer Settling Time and Acquisition Time)
A
= V
D
= V
(2)
V
I
I
I
IL
IH
IH
REF
IL
IH
®
+ = 5V 5%; V
I
REF
D
A
ADC7802
+) – (V
(3)
All Channels
(2)
V
REF
(1)
IL
IH
V
–) as low as 4.5V, the total error will typically not exceed 1LSB. (2) Faster signals can be accurately converted by using an external
REF
REF
A
V
V
REF
REF
+
–
V
+
D
–
V
REF
V
+; V
A
D
REF
– = AGND = DGND = 0V; CLK = 2MHz external with 50% duty cycle, T
Power Down Mode (D3 in SFR HIGH)
T
A
WR = RD = CS = BUSY = HIGH
CLK = 500kHz, 50% Duty Cycle
Logic Input Pins HIGH or LOW
CLK = 2MHz, 50% Duty Cycle
CLK = 1MHz, 50% Duty Cycle
High-Z State, V
= –40 C to +85 C, V
Between Calibration Cycles
Between Calibration Cycles
V
T
V
V
A
A
See Table III, Page 9
REF
T
REF
T
= V
= +25 C, V
A
A
I
SOURCE
+ = 5V, V
= –40 C to +85 C
+ = 5V, V
= –40 C to +85 C
CONDITIONS
I
All Channels
All Channels
High-Z State
SINK
D
T
V
T
A
REF
= 4.75V to 5.25V
A
V
500Hz
= +25 C
A
= 25 C
= 1.6mA
+
= 200 A
OUT
V
IN
REF
REF
2
D
V
= 0 to V
A
= 0V to V
– = 0V
– = 0V
IN
= 0 to V
D
D
D
4.75
4.75
MIN
–40
–65
4.5
2.4
3.5
0
0
8
4
4
ADC7802BP, ADC7802BN
Guaranteed
TYP
100
500
460
50
10
92
10
10
10
50
0.2
0.2
1/8
2
5
0
5
5
1
1
A
= –40 C to +85 C, after calibration
MAX
+150
5.25
5.25
100
100
100
+85
8.5
0.8
0.8
1.5
0.4
2.5
12
10
17
34
10
20
10
10
15
V
1/2
1/2
1/4
1/4
1/4
5
1
1
2
A
1
ppm/ C
ppm/ C
UNITS
mV/ s
LSB
LSB
LSB
LSB
LSB
LSB
mW
Bits
M
mA
mA
mA
nA
nA
nA
k
dB
Hz
pF
ns
ns
nA
pF
V
V
V
V
V
V
V
V
V
V
V
V
V
W
C
C
A
A
A
A
A
s
s
s
s
s