ADC10061 National Semiconductor Corporation, ADC10061 Datasheet - Page 9

• Manufacturer Part Number: ADC10061
• Description: ADC10061 - 10-Bit 600 NS A/D Converter With Input Multiplexer And Sample/Hold, Package: Soic Wide, Pin Nb=20
• Manufacturer: National Semiconductor Corporation

Functional Description
section of the MSB Ladder has
voltage across it, and each of the LSB resistors has 1/64 of
the total reference voltage across it. Tap points across these
resistors can be connected, in groups of sixteen, to the
sixteen comparators at the right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input
voltage. This estimate is then used to control the multiplexer
that connects the MSB Ladder to the sixteen comparators on
the right. Note that the comparators on the left needn’t be
very accurate; they simply provide an estimate of the input
voltage. Only the sixteen comparators on the right and the
six on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen compara-
tors on the right. For example, assume that the estimator
determines that V
estimator decoder will instruct the comparator MUX to con-
nect the 16 comparators to the taps on the MSB ladder
Applications Information
1.0 MODES OF OPERATION
The ADC10061, ADC10062, and ADC10064 have two basic
digital interface modes. Figure 1 and Figure 2 are timing
diagrams for the two modes. The ADC10062 and ADC10064
IN
is between 11/16 and 13/16 of V
REF+
and V
FIGURE 3. Block Diagram of the Multistep Converter Architecture
REF−
1
⁄
8
. Six comparators com-
of the total reference
(Continued)
REF
. The
9
between 10/16 and 14/16 of V
then perform the first flash conversion. Note that since the
comparators are connected to ladder voltages that extend
beyond the range indicated by the estimator circuit, errors in
the estimator as large as 1/16 of the reference voltage
(64 LSBs) will be corrected. This first flash conversion pro-
duces the six most significant bits of data — four bits in the
flash itself, and 2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the multi-
step conversion technique used in the ADC10061,
ADC10062, and ADC10064 needs only a small fraction of
the number of comparators that would be required for a
traditional flash converter, and far fewer than would be used
in a conventional half-flash approach. This allows the
ADC10061, ADC10062,
high-speed conversions without excessive power drain.
have input multiplexers that are controlled by the logic levels
on pins S
showing how the input channnels are assigned.
0
and S
1
when S/H goes low. Table 1 is a truth table
and ADC10064
REF
. The 16 comparators will
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perform