ICE1230 IC Ensemble, ICE1230 Datasheet - Page 25

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ICE1230

Manufacturer Part Number
ICE1230
Description
ac 97 Audio Codec
Manufacturer
IC Ensemble
Datasheet
Preliminary
Power Management ( continued... )
Test Mode Operation
ATE Test Mode: (PCB in-circuit Testing of the ICE1230)
ATE Test mode is entered when the SDATA_OUT signal is sampled at the rising edge of the RESET# signal.
In this mode, the SDATA_IN and BIT_CLK pins are placed in a high impedance (Hi-Z) state. This mode of
operation doesn’t occur under normal operating conditions.
Vendor Test Mode:
Vendor Test mode is entered when the SYNC signal is sampled during the rising edge of the RESET# signal.
This mode of operation doesn’t occur under normal operating conditions.
Rev. 1.3, 9/21/98
Figure 13. AC’97 Power Down Procedure with Analog Section Still Active
Note: To power up the codec, a warm reset is required; PR4 is reset to zero upon either reset.
Normal
PR0=1
ADC=1
PR0=0
&
ADC’s OFF
PR0
PR1=1
DAC=1
PR1=0
&
DAC’s OFF
PR1
PR4=1
Warm Reset
Digital I/F
OFF
PR4
Shut Off
ICE 1230
25

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